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Showing content with the highest reputation on 10/14/21 in all areas

  1. Feels like AS500 is a leet spelling of ass-oo...
    2 points
  2. I wouldn't say 'simply' either — the Hi-Toro Amiga/Lorraine dev team made the early Daphne video output unit out of wire-wrapped TTL logic, but there were several boards, and it was prone to failure, as were the Agnus and Portia units that were similarly built. And that Daphne had — let's say, "comparable" video output to VERA. So yes, it can be done. But it definitely isn't as simple as throwing together a few discrete components, unless all you want is the equivalent of a PET display. And that is not what our gracious host wants. If he did, he'd be satisfied to leave things to The Future Was 8-Bit and their Mini PET kit.
    2 points
  3. Indeed. The proof is in the pudding. If it's easy, go do it and show us the better more enlightened way. I know it is hard for some people to find time to do such things when writing, derailing thread topics, and fighting to keep foreign governments from making us appear foolish take so much otherwise productive time... It seems it would be a great investment for the world if one could take the Ben Eater world's worst video card and turn it into something comparable to VERA.
    2 points
  4. I don't know the details of the Vera implementation ... not only is the circuitry specification not public, but even if I had it, I would probably have to study up quite a bit in order to understand everything going on ... but one can speculate that with the dataport is driven by an 8MHz clock and Vera running an internal 50MHz clock, that Vera might access the SPRAM 3 cycles out of every four, and the fourth is when the SPRAM can accessed by the dataport. It also seems likely that it works with a rotating pair of rowbuffers, like the Gameduino ... one being used by the pipeline that generates the upcoming scanline bottom layer, intervening sprites, top layer, and any sprites on top, while the other one is being used to generate the current scanline ... and those would be in Block RAM as well, given that so much of data accessed by the video generation pipeline originates in the SPRAM. But while I am less than a beginner in terms of using FPGAs, I have seen the FPGA used for Vera quoted at under $7 Q1 at Mouser, and I have seen other FPGA with far more pins at over $20 Q1, so I am always a bit skeptical about confident assurances that "so and so" can "easily" by done when the "ease" may well involve simply throwing three times as much money at the problem.
    2 points
  5. From what they've said before, exactly ... 8 I/O pins connect to the data bus, 5 I/O pins connect to A0-A4, and from that I would guess three more pins allocated for chip select, R/W and PHI2, with all the lines from the 6502 level shifted to 3.3V.
    2 points
  6. after a long wait, Prog8 7.1 (beta version) has just been released. https://github.com/irmen/prog8/releases/tag/v7.1-beta Most of the changes this time are internal to improve code quality and testability. But several important bugfixes and enhancements have also been made. One thing to mention now is that the ``%target`` directive has been removed, the compilation target is set on the command line options. A full list of changes will be published on the 7.1 final release. In the meantime, here is the changes list since 7.0 https://github.com/irmen/prog8/compare/v7.0...master
    2 points
  7. Yes, it went up back in August. The name was wrong, though, so it was the "AS500." At the time, I was thinking, I didn't know IBM had released a follow-up to their popular AS400 mainframe..
    1 point
  8. After thinking to have understood the FPGA thing, I would not mind getting an X16 in FPGA only. I don't have to solder it. IMHO the success of such a project depends on the amount of the community. Getting the price down seems for me the most important part in the equation (having a physical thing instead of just an ARM based emulation). Could an FPGA for the early adopters have the option to "change the wiring" if it seems necessary to fix something later?
    1 point
  9. I have been on the fence about this for a long time, but now that it's back in stock here, it's a lot harder for me to ignore. The temptation is real, just becasue as much as I would love all original hardware, that's just not going to happen due to all the reasons I mentioned before. Sometimes, I hate my love of nostalgia.
    1 point
  10. Replying to @Scott Robison ... Prob only 5% of the fanbase here will be interested but if you look at Day 1 of VCF east (YouTube link), you'll see just that... Ben Eater's worlds worst video card implemented in FPGA by Stefany of C256 Foenix. The hour went by quickly but if you start with the basic of what Ben did in hardware and know what an FPGA is and is not, you can see her walk via verilog, and provide a start into what is required in order to make this wonderful fungible hardware behave in any way one desires. She gets nowhere near what she did with VICKY II (sprites, tiles, various video modes, Gideon SID, and everything else) but it's still interesting. Probably could have used an 8 hour workshop or a week of training/hands on. But in the absence of nothing, it was something.
    1 point
  11. A note on Impossible Mission on the Maxi. Once in the game, you can reset it and get a new map, by hitting stop/restore, or maybe just restore. Whatever the sequence is, you can get a random map. Just got my Maxi a couple days ago, and that's one of the first things I fiddled with, lol.
    1 point
  12. One interesting point is whether it's timing as designed will play nice with a 16MHz Z80 bus, since a 32byte register address range fits well with the 256byte I/O address space of the Z80. Use a 2->4 decoder to select Vera on I/O (a6,a7)=%00, select tri-state hex latches on %01 and %10, tie the Vera SPI select to the output enable of the %01 latch to select from four SPI devices, tie the other latch to select a 32K memory bank on a 512KB SRAM, and it could make a really cute little CP/M Plus system to play with ... two SD cards, one UART and an I2C bus master for parallel port, keyboard, etc.
    1 point
  13. "Yes" the Maxi is worth it. Especially now that you can get it on Amazon in the U.S. Yes you can save programs but you can also save 'state' of 4 'virtual' machines (I believe it's 4). And you can download any d64 image from the internet and run those programs and games so regardless of what comes built in, you have access to nearly everything. Space Taxi, Spelunker were two that I always liked and I recently got my hands on them. Scott mentioned that Impossible Mission runs 'correctly' if you run it from a D64 image (USB thumb drive plugged into the side). As packaged, the Impossible Mission maze is 'fixed' vs being dynamically generated. This might apply to other games as well. Anyway, this is my opinion. You can mess around with Rasp Pi's if you are looking for science projects and distractions, I suppose there is an element of satisfaction in doing so if that's your jam but if you owned a C64 in the 80s, get the Maxi because it's the same experience. If you are unconvinced, jump on YouTube and search for Robin's excellent reviews and deep dives on the Maxi (8 bit show and tell). But take this test... watch this video for 1 minute and decide if you would rather do that or use a non-standard keyboard (aka no PETSCII characters on the keyboard), or if you'd just rather use a C64. https://retrogamecoders.com/raspberrypi-bmc64-c64/
    1 point
  14. I think the same thing. More than that would mean a lesson in 65x logic design, which could be a thread all of its own.
    1 point
  15. Vera doesn't rely on the Block RAM for the "Vera Video RAM" space, it uses an internal 1MBit SPRAM module, accessed as 128KB, and it is indeed vital for the functioning of Vera for it to access it faster than 8MHz. I guess it might use Block RAM for the FIFO buffer for the PCM. And, yeah, I expect that for the 512KB High RAM, an FPGA with enough I/O pins to access a 512KB SRAM might be less expensive, but it seems like it would be pricier than the FPGA they use for Vera.
    1 point
  16. Pretty much. I don't remember seeing the interface details published, but it should be similar to a 65C22 VIA. It's a bespoke digital design. The logic building blocks inside the ICE40UP5K are pretty simple, mostly D flip-flops in various flavors and 4-input look-up table cells which can do any arbitrary 4-bit logic function. The full cell library is specified here: https://www.latticesemi.com/view_document?document_id=52206 Almost. 1.2V is the core voltage. There is a second power rail for the IO, 3.3V for Vera. The FPGA has internal level shifters between the core and IO rails. External level shifters are needed to interface the 3.3V Vera IO to the 5V X16 logic.
    1 point
  17. There are different FPGA with differing capabilities. Not all are such low power, though mostly I think yes, you would need level shifters to interact with a 5V bus. For communication between a physical CPU and the FPGA (or really, anything interacting with the FPGA), your HDL defines a number of externally exposed IO lines to serve whatever purpose you want. For example, I have a Nexys 4 DDR board that exposes 40 pins to the outside world (and more IO is assigned to other IO devices on the board itself, such as switches, 7 segment displays, LEDs, network, VGA, etc, etc, etc). Some FPGA have a CPU sitting next to the FPGA, or IP is available to embed a soft core CPU into the fabric of the FPGA. Others just provide the FPGA and a processor (if desired) has to be created from scratch or sourced from another project or offering.
    1 point
  18. When the conversation about the final release plans of a modern retro computer has turned to what technically constitutes a “computer” and a “program”, the plot has truly been lost. Something tells me that Murray and company learned all they needed quite some time ago.
    1 point
  19. Lattice ICE40UP5K in the 48-pin QFN. https://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus The datasheet: https://www.latticesemi.com/view_document?document_id=51968 Lattice's iCE40 family is a good place to start exploring FPGAs. They are a good deal simpler than most offerings from Xilinx and Intel.
    1 point
  20. I think this thread has jumped the shark. Perhaps it needs to be locked, too.
    1 point
  21. @geek504 Hi glad you asked, lets answer this here I started working on it about three years ago. I wanted to learn how to create a programming language, a parser, and a compiler (I have written several interpreters over the years but never an actual compiler) . I started implementing it in Python but as the project grew larger, switched to Kotlin as an implementation language because it became too unwieldy to constantly refactor it in Python even with IDE support. Because I like retro computing and the Commodore-64 in particular, I thought it would be fun to try to target that platform to be able to write programs for it in a medium/high level language. With the possibility to directly access the hardware and use inline assembler code when needed for the nitty gritty stuff. Only recently I started adding CommanderX16 support into the compiler. Prog8 the language itself is essentially a C like langue but with heavy Python influences because I really like Python. It would be cool if people would use Prog8 for larger projects, but other than the few dozen example programs I've not actually written a large piece of software in Prog8 yet Mostly because I'm still too busy tinkering with the compiler itself and fixing bugs, and now, CommanderX16 support for it.
    1 point
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