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  1. That, as well as additional features and changes to existing features, of the VERA architecture.
  2. 1. (zp),X isn't a valid addressing mode. You have (zp),Y and (zp) without indexing on 65C02. 2. You never INX (or really, INY) between each STA instruction, resulting in (eal)+0 to be written with eah instead of eal, and (eal)+1 won't be written at all. Here's my version (compatible with all 65xx systems): LDY #0 LDA eal STA (eal),Y INY LDA eah STA (eal),Y
  3. I don't see your document mention the default palette RAM values on reset.
  4. Don't forget that bit 3 (value $08) is used to make the address stride decrement instead of increment.
  5. You can optimize an LDr #0 / STr pair into an STZ instruction, as long as the addressing mode for the store instruction is ZP, ZP,X, ABS, or ABS,X. If you're using the zero loaded in the register r as a value to pass to a subroutine (e.g. LDA #0; STA address; JSR subroutineThatTakesOnA), you could omit the STZ optimization for easier porting to an NMOS 6502 system. X and Y can now be pushed or pulled. On an NMOS, this requires the X or Y register to be transferred to the accumulator before pushing, and transferred back after pulling. You can branch relative unconditionally with the BRA instruction in the same way as any conditional branch, like what you used accidentally. You can increment or decrement the accumulator, while an NMOS can only increment/decrement X, Y, or memory contents. Slithy pointed out that CA65 just takes plain INC/DEC without an operand specified, but some other assemblers accept A as the operand, and others use the mnemonics INA and DEA. The 65C02 also adds #IMM, ZP,X and ABS,X modes to BIT. On an NMOS, testing with a immediate requires the byte to be stored in a literal pool in memory, or the AND instruction to be used at the cost of destroying the value in the accumulator. AND'ing or OR'ing directly on memory can be done with the TRB and TSB instructions. Just discard the Z flag (the result of BIT) and back up the accumulator whenever needed. Remember that TRB takes the inverse of the value in the accumulator, but TSB doesn't. There's also a (ZP) mode added to all instructions that have (ZP,X) and (ZP),Y. This prevents the need of setting X or Y to zero. For example, I can write a MEMCPY implementation (basically emulates LDIR in Z80) with the source and destination pointers in zero-page, and a 16-bit loop counter in X and Y. If this were an NMOS, I need to put one (or even both) halves of the loop counter in the zero-page. There's also a JMP (ABS,X) instruction added, which is very handy for jump tables. There's also zero-page-only bit test+branch (BBR, BBS) and manipulation (RMB, SMB) instructions. These were initially only on Rockwell models before they were merged into the WDC design. You won't find these on a 65816, even though it has all other 65C02 instructions. These can't be found on 65C02's from any other manufacturers. WDC models also have the WAI and STP instructions that set the processor to a low-power state. The former stops execution until any interrupt occurs, and the latter stops the processor only until a reset occurs. No other 65C02's have these. The 65C02 also fixes well-known NMOS bugs such as the infamous JMP ($xxFF) bug and the decimal mode flags bug. Some cycle counts were also changed. Is this information helpful for you? Because I still see you LDA #0 before STA and such.
  6. You don't necessarily have to store all of your sprites in VRAM at once. If you only have one sprite on-screen that uses those 17 frames of animation in the screenshot you posted, just keep one of those animation frames in VRAM at a time and copy the next one from RAM to VRAM when needed. However, this will impact performance.
  7. I thought the YM3012 was just used to convert the digital audio bitstreams from the YM2151 into analog audio outputs. Like, the CPU wouldn't be able to address it.
  8. The YM2151 has more channels (8 versus 6). The YM2612 has only 6 channels and not 7, as the DAC shuts off the 6th FM channel. Both of these have 4 sine-wave operators per channel, and include 8 different ways of combining these operators together. The YM3812 is a 2-operator chip that supports 3 more waveforms, and 9 channels. The chip could be switched into a mode which replaces the last 3 FM channels with 5 channels of unique percussion sounds controlled with the FM channels' patch registers. This means the chip can produce up to 11 channels of sound at once.
  9. But @Frank van den Hoef did confirm in another thread here that an LFSR is used in the hardware HDL. He didn't give any specifics though, like the LFSR's width and what taps it uses, or if it's shared or per-channel.
  10. Has the VERA PSG's noise LFSR algorithm been revealed yet? It's not implemented in the emulator's PSG code as far as I'm aware.
  11. How is this a coincidence? What am I missing?
  12. I guess because it has 16 PSG channels?
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