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Wavicle last won the day on November 12

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  1. Is this the Z-machine you are talking about or am I missing something?
  2. In terms of interfacing parallel 6502 to a microcontroller, I would strongly recommend the MCP23017 I2C GPIO extender. Pretty much all microcontrollers have I2C hardware and that GPIO extender gives you 16 GPIOs for $1.70 in single unit quantities. I used the SPI version of this IC (MCP23S18) in my YM2151 test harness for verifying whether or not sketchy chips that I get from China are really YM2151s or not. Its inputs are 5V tolerant so it also protects the Raspberry Pi that runs the test program from any surges caused by a bad IC (like if maybe the IC is a boost converter or something - much easier to sacrifice a $1.70 part than a RaspberryPi which can be difficult to come by these days).
  3. I don't recall exactly how much power it used. I believe it was around 250mW before I added the YM2151 circuit. That old IC consumes about 130mW by itself. The process of building the X16 on a breadboard was straightforward from a circuit design standpoint, a bit tedious and long from a "cut and strip wires" standpoint, and incredibly complex from a debug and signal integrity standpoint. I would joke at the time that if I walked into my office in the morning and didn't look at the breadboard 16 in a way that it approved of, I would spend the rest of the day with the oscilloscope debugging why it wasn't booting that day. The parasitic capacitive and inductive effects were huge.
  4. An X16-compatible computer on a breadboard is doable -- even at 8MHz. I wouldn't recommend it to anyone without a lot of experience debugging signal integrity issues. Back in April I had an essentially complete X16 compatible computer on a few breadboards.
  5. I can't find a supplier still making a 16550, but this TI chip is fairly similar and still being made: TL16C2552FNR Texas Instruments | Mouser
  6. I am not sure what you mean. VERA uses an external 25MHz clock. It is used by VERA as a pixel clock, but due to physics and the FPGA's construction, it will be slightly out of phase with the VGA pixels.
  7. I don't think you understand: I have already looked and saw no end-to-end solution currently available. If you have something that can cast VGA over the internet, pass a GPIO or two, multiplex an SD card, and translate remote keystrokes and mouse movements to PS/2 - let me know. I can figure out the rest. Otherwise, the best option was basically a RasPi acting as a webcam and some ad-hoc ESP8266 remote keyboard thing I had found at one point, and pricey and no longer available SD multiplexer.
  8. The good news is that there is also a PR for an emulator update that moves keyboard and mouse to I2C fetches. The other good news is that I do not think this NMI problem exists on the hardware. If an NMI hits when retrieving the keyboard status from the SMC, it will just cause that I2C clock to get stretched.
  9. PS/2 was moved to the SMC this past summer. A pull request to bring this into the kernel proper is in process: Move keyboard and mouse to I2C interface by jburks · Pull Request #338 · commanderx16/x16-rom (github.com)
  10. Do you have suggestions for these? I have several functional X16 boards here. I've pondered this for several months but always hit a roadblock on the remote keyboard and filesystem.
  11. There are no available IOs on the FPGA to provide this signal.
  12. There is only one FPGA on the board. It's in the video card and there only a handful of spare bits in the register space remaining. No unused bytes exist within VERAs register space. I think the cheapest way to do this if it ever becomes necessary is weakly pull up or down some of VIA1's dedicated output pins, put those pins in read mode, and then read out the results of the pull resistors.
  13. Computers got by with no built-in ethernet and pushing that functionality off to an expansion card until well into the 32-bit era. Still today the highest performance networking solutions come as PCIe expansion cards. It doesn't seem like an 8-bit computer needs to come ethernet ready out of the box.
  14. The solution to address the problem was addition of a clock stretching circuit. It could be done with a parallel bus latching circuit, but I think you're understating the design complexity. You need at least two latches, one for the data bus and one for the address and control signals, a bus transceiver to prevent the logic on the slow side from driving the data bus, and the logic to detect/decode accesses to those. Potentially 4 ICs plus a complex software interface scheme... or we could stick with clock stretching circuit which uses a single IC and is transparent to software.
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