Jump to content

Wavicle

Members
  • Posts

    158
  • Joined

  • Last visited

  • Days Won

    8

Wavicle last won the day on April 27

Wavicle had the most liked content!

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

Wavicle's Achievements

Enthusiast

Enthusiast (6/14)

Very Popular Rare Conversation Starter Rare One Year In Reacting Well Dedicated

Recent Badges

154

Reputation

  1. The available emulator runs on RPi. It's a bit slower than a desktop PC, but it runs. I modified it to redirect VERA IO to a GPIO expander for testing my breadboarded VERA:
  2. 6.29375 = 25.175 / 4 25.175 is the pixel clock for 640x480 VGA. Each of those 31.5kHz scanlines has 800 clocks and 1/4 of that would be 200; so it is also 200 times the 31.5kHz horizontal frequency. Using divisors, especially power of 2 divisors, of a single master clock within a single design allows you to have essentially a single clock domain; this allows you to avoid implementing complex clock-crossing FIFOs for every signal that has to move between the fast and slow domains.
  3. Removing 3 RAM chips and the support demux also saves considerable board real estate. No telling which way Kevin will take the official board, but the prototype PCB for my design left them out to save on board space and fit the whole thing into a mini-ITX form factor. I left a header and jumper for expanding the RAM if I ever felt the need. $20 extra in BOM cost does not mean $20 extra in sticker price - I hope everyone realizes this. When you start manufacturing these things you have to add margins to account for production losses (bad components, bad boards, customer returns, and on, and on).
  4. I created a BOM on Mouser that contained most of the motherboard ICs, and several other big ticket items, hopefully it will paste here correctly. Parts that it does not contain include: YM2151, YM3012, VERA, passive components, PCBs, Mouse, Keyboard, Case, PSU, or SNES sockets. This is for my compatible design which is known to differ from the official design by at least 1 74xx IC. Mouser # Manufacturer Description 652-4607X-1LF-10K Bourns Resistor Networks & Arrays 7pins 10Kohms Bussed $0.56 $1.12 955-W65C02S6TPG-14 Western Design Center (WDC) Microprocessors - MPU 8-bit Microprocessor $10.75 $10.75 806-KMDGX-6SGP-S4N Kycon Circular DIN Connectors 6P/6P PC99 GRN/PURPL STACKED GOLD PLATED $2.41 $2.41 490-SDF-60J CUI Devices Circular DIN Connectors 3 13 Positions, Receptacle, Right Angle, Through Hole, Shielded, Standard Circular DIN Connector $3.19 $3.19 520-TCH357-X ECS Standard Clock Oscillators DIP-8 5V 3.579545MHz $2.90 $2.90 571-1-1775099-3 TE Connectivity Power to the Board ATX PWR CONN 1 BDLK 24 POS $0.92 $0.92 595-TL074ACNE4 Texas Instruments Operational Amplifiers - Op Amps Low-Noise JFET-Input Op Amp $1.12 $2.24 579-MCP7940N-I/P Microchip Real Time Clock I2C GP RTCC,64B SRAM $0.94 $0.94 556-ATTINY861-20PU Microchip 8-bit Microcontrollers - MCU 8kB Flash 0.512kB EEPROM 16 I/O Pins $2.85 $2.85 595-SN74LS06NE4 Texas Instruments Buffers & Line Drivers Hex inverter Buffer/ Driver $0.86 $0.86 595-CD74ACT139E Texas Instruments Encoders, Decoders, Multiplexers & Demultiplexers Dual Line $0.93 $0.93 595-SN74AHCT04N Texas Instruments Inverters Hex $0.71 $0.71 595-CD74ACT20E Texas Instruments Logic Gates Dual 4-Input $1.03 $2.06 595-SN74AHCT02N Texas Instruments Logic Gates Quad 2-Input $0.71 $2.13 595-CD74ACT163E Texas Instruments Counter ICs Sync Preset Binary w/Sync Reset $0.99 $0.99 595-SN74AHCT74N Texas Instruments Flip Flops Dual w/Clear Preset $0.73 $0.73 815-ACH-16-EK ABRACON Standard Clock Oscillators XTAL OSC XO 16.0000MHZ HCMOS TTL $2.71 $2.71 595-SN74ACT10N Texas Instruments Logic Gates Triple 3-Input Positive-NAND gates $0.74 $0.74 595-SN74AHCT32N Texas Instruments Logic Gates Quad 2-Input Pos $0.73 $0.73 595-SN74AHCT138N Texas Instruments Encoders, Decoders, Multiplexers & Demultiplexers Line Decoder $1.01 $1.01 595-SN74AHCT273N Texas Instruments Flip Flops Octal $0.81 $1.62 804-39SF0407CPHE Microchip NOR Flash 512K X 8 70ns $2.24 $2.24 913-AS6C1008-55PCN Alliance Memory SRAM 1Mb, 2.7V-5.5V, 55ns 128K x 8 Asynch SRAM $3.99 $3.99 913-AS6C4008-55PCN Alliance Memory SRAM 4M, 2.7-5.5V, 55ns 512K x 8 Asynch SRAM $6.38 $25.52 955-W65C22S6TPG-14 Western Design Center (WDC) I/O Controller Interface IC Versatile Interface Adapter $10.15 $20.30 571-1-5530843-8 TE Connectivity Standard Card Edge Connectors CONN SEC II 60 POS 100C/L $5.29 $21.16 $115.75
  5. This is a target that is moving uncomfortably fast in the opposite direction of where they normally go. The FPGA, CPU, and VIAs have shot up ~50% in the last 3 months. The BOM for VERA last month was $30.14 for parts in bulk or $37.73 when buying enough for a single board. I did a pre-price-spike BOM for Breadboard16 back in April; it was $259.72 for everything or $124.92 when costs for things like the solderless protoboards are removed. These prices are for a 512K system and are missing: Mouse, Keyboard, Case, PSU, expansion slots, IEC connector, and SNES sockets. Accounting for the price increases, parts only, including motherboard (~$20 for a 4-layer mini-ITX form factor board) and VERA, comes to around $160 for a 512MB model. PSU is another $25. Case is maybe another $50-75. Keyboard and mouse depend on your preference, say another $25. COTS total comes in around $250-$275 for a base model system. Some broke college kid's time to solder everything together is probably another $150 (7.5 hours x $20/hour), or another $300 if you hire your cousin who can do it "for free". In all honesty, every time I look at the total, I wrinkle my nose and ask "how??", then I look at my BOM with part cost broken out and realize it's just a LOT of parts that cost between $0.50 and $10.00.
  6. $6-$8 for SRAM + $10 for the FPGA with more IOs + shipping + tax + additional development time. The increase in part cost does not usually represent the cost increase to the end user cost. Factors such as yield, R&D cost, and profit have to be factored in as well. Increasing the VRAM is going to increase the total cost of the VERA board by at least 50%. For a point of reference, I have two assembled, tested, and working VERA boards and most of the parts I need to build 8 more (just need to order new PCBs because the SD card socket is no longer available). Even though my part cost per finished board is around $27, my total outlay to get here is close to $500 - just for VERA. (I'm in for about another $800 on the parts used to build my X16 on the breadboard.) Hardware development is expensive (but fun, so there's that).
  7. For reference, here is a BOM I worked out for a single VERA (except for the PCB which is prohibitively expensive to buy a single unit, but the price comes down quickly in bulk, so I priced it as 1/15th of a 5 panel, 15 board order) using prices as of today at Mouser: VERA_BOM_2022_Jun_05.tsv (github.com). I know this is a project with international appeal, but to simplify on my end, all prices are in $USD. Base board (voltage regulators; bus interface; FPGA; clock; passives): $23.12 VGA: $2.85 Composite + S-Video: $5.15 PSG Audio: $3.52 SD Card: $3.09 Total part cost: $37.73 + tax + shipping. Does not include assembly, test, yield loss and things like that. Using bulk pricing of ICs in 10-24 unit quantities and passives in 100-249 unit quantities, total part cost is $30.14 (+tax +shipping). Now, if we circle back to the question of what would it take to get more VRAM, a larger FPGA would add about $10 and external VRAM would be about $8 for 512K (~$6 for 256K).
  8. The iCE40UP5K has 128K of SRAM on the die. It's an usual feature in a $6 FPGA (now $9, thanks to the chip shortage); normally a design would go off-chip to a dedicated SRAM IC, but by using this FPGA that was not necessary. This keeps costs down but also limits expansion since there are no available IOs to interface with an external high speed SRAM component. 128K is double the addressable memory of the 6502 so it feels to me like it is sized right for the intended product. Even at 8MHz, writing a 320x240x8bpp bitmap to VERA is already a fairly slow affair.
  9. I can't think of a reason why repurposing those bits for alpha blending wouldn't work. The only caveat I can think of is that all of the hardware multipliers have been allocated to other functions. With only 16 possible levels of alpha, you can probably do the blending as 16 different logic cases without the need for a multiplier. I seem to recall a little over a year ago I prototyped a 12 bit color alpha blending design on an FPGA using some clever bit shifting. I think it gave me alpha levels of 1/(2**n) and 1 - 1/(2**n) (i.e. it had 50%, 25%, 12.5%, 6.25%, ... as well as 75%, 87.5%, 93.75%, ...). My recollection was that with 12 bit color, only 87.5%, 75%, 50%, 25%, and 12.5% were of any use. My opinion at the time was that hand picking 16 different alpha levels would yield much better results.
  10. I looked into adding alpha after VERA was first opened. Unfortunately with the current design, the bits in the line buffer that would be used for sprite transparency are used for sprite collision. Supporting per pixel transparency would mean giving something else up.
  11. The decision is ultimately up to @Michael Steil. He's an approachable and reasonable person though, so if your changes correctly document the code and focus on documenting functions that need it (as opposed to every single line that is sometimes seen in assembly code), I think they would have a good chance of getting merged. Michael's favorite response anytime anybody suggests fixing something in the ROM is: "Pull request?"
  12. I'm most curious about how viral the license is intended to be. There are X16 Enthusiasts here making tools and game engines for others to use. Some of those could end up in the form binary library object files. Linking against a vbcc-compiled library will implicitly include binary data produced by vbcc into that project without the library user ever touching vbcc. Will the non-commercial licensing restriction then infect that project, or stop at the library? Well-intentioned library authors need to know if there is an implicitly viral license that library users will need to be aware of.
  13. Yep! Thank you clarifying that. I believe that I've fixed the Verilog causing this and sent a PR to Frank for consideration. (https://github.com/fvdhoef/vera-module/pull/11) For all those not on Discord here are before (current VERA design) and after (VERA design w/ my sprite priority fix) photos rendered on real hardware (with hand-drawn red circled areas where sprites were hidden because the scoreboard background sprite was rendered on top of them):
  14. I have another quick update for this thread on progress with the SD card issue: The short version is: I've never seen my "Breadboard16" fail to recognize an SD card as seen in the update video from last August. VERA will usually not come out of reset if an SD card is plugged in, but this is an electrical problem between the SD card SPI lines and the FPGA configuration flash SPI. (The v4 VERA fixed this by adding a digital switch that disconnects the SD card from the SPI bus until after the CDONE signal from the FPGA.) In fact, @Frank van den Hoef's VERA design and FAT32 code has been remarkably reliable (as long as files are named using only uppercase, that's a limitation of the original CBM code though). I've asked @Michael Steil about his SD card experience as well and he also has never encountered this issue. I livestreamed my youngest playing both FlappyX16 and Chase Vault on my Breadboard16 compatible hardware to a small audience on Discord tonight which included @ZeroByte (author of FlappyX16) and @SlithyMatt (author of Chase Vault) and we all learned a bit about the differences between the hardware and the emulator and flagged some interesting corner cases for follow up (notably that the emulator significantly overestimates the available work units for sprite rendering in the hardware). In any case, I've emailed David Murray about the details of his SD card because at this point I'm suspecting the problem is his card more than the X16 hardware or software. Hopefully it doesn't end up in his spam folder!
  15. I probably need to update this thread now that my Breadboard 6502 "X16 Compatible" is nearing completion, after adding the audio components, the power consumption shot WAY up. Currently at 4MHz with both VERA and YM2151 generating audio, I'm measuring 500mA - or about 2.5W. I don't have the tooling to measure component-by-component to see where all that power is getting consumed, but it jumped after the Audio, OpAmps, and DACs were added. The YM2151 is warm to the touch (not hot, but not room temp either) so I figure that's one major culprit.
×
×
  • Create New...

Important Information

Please review our Terms of Use