Jump to content


  • Content Count

  • Joined

  • Last visited

Community Reputation

30 Excellent

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. It's a nice feature but I wonder if it is worth the two expansion slot pins. Did you consider the PC motherboard way, a pin header and CD-audio cable? Same here. I can't muster even a little nostalgia for it.
  2. Read the datasheet before answering. Good idea... yeah, it's probably not the probe. Maybe a bad ground?
  3. This is application and expansion card dependent, so I don't see a need to be too prescriptive. The main requirement is that every DMA controller needs a "DMA enable" register whose reset state is disabled. DMA controllers may take the bus only when enabled and software may enable only one DMA controller at a time. The application can decide on enable scheduling in multi-controller situations. The main point expansion card designers need to know is that multi-controller arbitration is software, not hardware controlled. I still say using SYNC is better than using /ML. It costs the same and avoids adding restrictions like "don't access Vera auto-increment registers if a DMA controller is enabled". That's a nice improvement over proto#2.
  4. Here is my speculation: It's the low impedance of the scope probe. Try switching to 10x mode.
  5. I think you always need to halt the CPU with /RDY and you always need to tri-state the busses with /BE. Can you give an example when both are not required? This attempt at self-arbitration won't avoid bus contention when two DMA controllers want access on the same cycle. Without real hardware arbitration you are left with enabling one DMA controller at a time through software. There is nothing wrong with software arbitration but it renders this /ML business pointless. I think I mentioned in another thread that it looks unsafe for DMA controllers to interrupt writes to auto-increment addresses. An easy way to avoid this problem is to take the bus only during opcode fetch (by monitoring SYNC). As a bonus, this inherently avoids breaking atomic operations so /ML is no longer needed. Also note that because /RDY is directly driven by the DMA controller it is impossible for DMA controllers to address anything that uses /RDY to add bus wait states. It is nominally 62.5ns, but what is the duty cycle spec on your crystal oscillator? +/- 5% is pretty typical unless you pay extra for better. Or did you switch to a 16MHz oscillator and divide it by 2 to square things up?
  6. Yup. That matches my guess exactly. I did not see anyone from the design team confirm this but I can't think of any other parts that match. The 16Kx16 SPRAM has just one address port so I would call it single-port and leave it at that. But that is picking nits. I think we both agree that it is definitely not "truly dual-ported". Hence the request for citations...
  7. Right. I omitted that intentionally, which makes it all the dumber. I was thinking applications would schedule writes on their own. But the schedule would be for blocks of writes, not individual ones. Thanks for the correction. Anyway, I suppose it is possible reads are working on the bench but that is almost worse. It is much better for things to be broken-broken, not sometimes-broken or sometime-in-the-future-broken. It would suck to have a batch of slow parts causing sound problems halfway through a production run. It's even worse if the slow parts break a bunch of DIY kits.
  8. Those are logical ports, and maybe that is what Bruce meant by "truly dual-ported". I inferred he was describing the internal construction of the FPGA RAM blocks.
  9. Exactly. Gating the raw decoded chip select with PHI2 obviously puts /CS well after PHI2 rise. They missed the setup window. Controlling only the YM2151 /CS is sufficient. All of the data timing parameters reference the last control signal change. Zero wait state operation isn't so easy at 8MHz. Access time is 180ns so reads are totally broken. But those are used only to check interrupt status. Interrupts might not even be connected. The easy fix is to simply disallow reads. Zero wait state writes cannot meet the timing requirements by using PHI2 edges for pulse forming. Using the typical design pattern will violate Tcw(100ns) and Tds(50ns). That probably works fine on the bench at room temp but may not be reliable across a production run. Some kind of /CS pulse stretching is needed to satisfy the datasheet requirements. After the VIA timing problems I imagine the team reviewed every chip's timing requirements, and have a plan to address this in proto#3. Or maybe they just plan to screen YM2151s before using them. Do such versions exist? I have never encountered a reference that suggests this, let alone a datasheet that quantifies the timing differences.
  10. That's not an unreasonable intuition but TTL doesn't work that way. Timing is an interesting subject. If you are interested in testing your understanding, can you explain which violated timing parameter Adrian fixed on proto #2?
  11. Yes, TTL and CMOS have different specifications for low and high voltage levels. Let's assume a minimum VCC of 4.5V for this example. For the F521, a "1" at the output means a voltage greater than 2.5V. This is the VOH(min) parameter in the datasheet. For the AC11032, a "1" at the input is guaranteed to be recognized only if the voltage is 3.15V or greater. This is the VIH(min) parameter in the datasheet. So a perfectly valid "1" for the F521 could be wrongly interpreted as a "0" by the AC11032. Obviously that would be bad. If you ever wondered why there are both AC and ACT logic families this is the reason. ACT input voltage thresholds are shifted downwards to be compatible with TTL output voltages. This article has a more complete explanation: https://www.allaboutcircuits.com/textbook/digital/chpt-3/logic-signal-voltage-levels/ As an aside, in your last schematic you could connect RW to that unused 'F521 input and save some glue logic.
  12. Replace the '574 with '273, and use its built-in clear function. Be careful mixing logic families. 'AC11032 VIH is not compatible with 'F521 VOH. You can replace all of the jelly bean logic used to generate both bank register clocks with a single '138, similar to BruceMcF's comment above.
  13. Geez, where is my head? Bank registers need to be initialized at power on. That is easiest using a resettable flop, like the '273.
  14. Right, CLK and D are the only inputs that affect flop state. OE only connects or disconnects the flops' outputs to the '574 outputs. The logic diagram on page 2 of the data sheet illustrates this pretty well.
  • Create New...

Important Information

Please review our Terms of Use