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BruceMcF last won the day on July 10

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  1. But popping a 65816 into the CPU socket won't add the "one extra chip", because it has to be in the motherboard. Popping a 65816 into the CPU socket in effect gives you a 65802 with slight bus incompatibilities (SYNC is replaced by VDA/VPA and IIRC the clock outputs are DNC and a reset input). And a bus mastering 65816 card would be pretty much the same thing, though more room for circuitry to bridge the bus incompatibilities ... including masking out the bank address from the data lines. I would be entirely unsurprised if the problem in writing VERA is the bank on the data bus followed by the data confusing Vera in a way that is not an issue with the 65C02 write cycle. Nor would I be surprised if the bus cycles for some of the chips "work" with the 6502 but just make it, and small variations in actual read or write delays associated with the transition between bank mode and data mode make the timing too tight to work. But if you can get a bus mastering card to work, you get the pcode interpreter with the accumulator in 8bit mode and indexes in 16bit mode, with ops ending with JMP NEXTOP or an eight byte NEXTOP macro: NEXTOP: INY : LDA 0,Y : TAX : JMP (OP1,X) The thing is: since it can run 6502 assembly code, can run the same pcode as the 6502, except faster, and can host a compatible ROMBASIC interpreter, except faster, and since assembly code can test whether it is running on a 6502 or 65816, it might actually work as a 3rd party enhancement. Then it would only breaks running CX16 code if people use any of the four individual-bit-addressed operations in their assembled code, so it just needs "enough" of an install base so people shy away from doing that.
  2. Well, it IS a bit subtle, in that in one possible logical branch, if storing the Kernel bank number into $0001 does nothing, that requires a specific Basic ROM binary, so that we know exactly which values are where ... and the Basic ROM binary is subject to change. But while the Basic ROM binary is subject to change, if it DOES change, then the system will be Revision 39 or later, and storing $0001 will in fact take you to the Kernel bank, where the "mist" signature is stable between revisions. I didn't actually catch that until the second time I thought about the code.
  3. Now, I should stress that I was not engaged in a serious design proposal up there, but rather playing a less than totally serious what if game that "just coincidentally" ended up with something like a CX16 memory map. But, yeah, it's text manipulation or some other 8bit oriented date in any event -- it's not oriented to video -- given that the notion of single word Unicode has pretty much universally given way to UTF8 ... and it would have to be something that is leveraging the fact that there are VERY FEW TRANSISTORS in the 6502 hardware design ... so it's got to be a whole hell of a lot of 6502 cores on a chip ... so in that respect more like an array of GPU cores in some GPU designs, but targeting a text processing rather than video processing dedicate application. So it really is a 6502 core with 512bytes of on-chip cache as dedicated zero page and stack page, taking advantage of the very small hardware footprint of the 6502 to be able to give it much more persistent local storage than is typically feasible with a processor array chip design ... and then the L2 cache is shared out between the cores somehow ... say, locations $0000-$0007 are byte L2 segment registers for the 64K address space in 8K segments, giving up to 2MB L2 cache. $0008/$0009 controls whether they are R/W, Read Only or Write Only, so that an individual bank can be used as a pipeline between two cores. Actual RAM is accessed using a DMA controller accessed in the zero page address space of "one in N" of the 6502 cores, which controls the reading and writing between the L2 core and RAM. All quite implausible, but fun to think about.
  4. The "you" here is not you in particular, its the Commonwealth English "one". I meant the stable "mist" signature is four bytes that are positive and non-zero, so to test a single flag as soon as you load, as the code quoted by @Greg King does, you need a zero in the parallel position in the Basic bank (or else a byte with b7 set so you can use "BPL", but a zero works). That just happens to be the case at $FFF8 in Bank4 ... that's why it used $FFF8 and not the starting point of the signature.
  5. You need an address that has a zero in the Basic Bank in R38 (whether it's R39 or later is not an issue, because if you get to the Kernel bank, the "mist" signature is stable.
  6. Though it doesn't have to be future proof ... it's only a bridge until R39 becomes the baseline release. That's the part that has me in suspended animation ... I am not interested in putting code into a version test that I am going to want to strip out again once R39 is the public release.
  7. Quite, using ADC for both ADC and ADD, SBC for both SBC and SUB means there are two operations that simply don't have to be provided, which is even more transistors saved. Similarly, arithmetic shift right is less commonly needed, and if it is can be done by a routine, so leave it out.
  8. An example of that is how the subtract function is simply use the add circuit, but inverting the bits of the byte being subtracted. But without inverting the carry flag. "But that is not the two's complement negative, to get the two's complement negative you need to add one!" Oh, yeah, so for subtract, you set carry for borrow clear. If there is a borrow, leave carry clear for borrow set. "But that makes no sense, that makes the borrow flag the inverse of the carry flag!" Yes, exactly. And saves the transistors needed to invert the carry flag. "But the CMP instruction needs to subtract too?" Yes, and it needs to subtract with borrow clear. It doesn't care whether that sets the carry input to one or to zero.
  9. Access to the 2MB of L2 RAM cache and 1MB of L2 instruction cache is straightforward ... you put a byte into $0000 in the address space to select an 8MB segment of L2 cache, or 16MB segment of L2 instruction cache, and reading the associated bank window copies the L2 contents into the L1 cache, 64bits at a time. Writing is more involved (why only one window is R/W and it's the 8KB one) but each write sets a bit in a 1KB written value register, which sets a bit in a 128byte written 64bit word register. When not reading the L2 R/W cache, it scans through the written word register and does a write back of new contents, 64bits at a time, controlled by the written value register. Each core has its own 64KB L1cache, but the L2 cache is common to all cores, so only core 1 has the memory controller registers in its memory mapped I/O space.
  10. Actually this gets to the only point of taking a processor with such a small transistor footprint and speeding it up like that, which is that the bulk of the mask is taken up by some other specialized circuitry. One problem with that approach is less technical than economies of scale ... making the specialized circuitry so that it goes onto a bus to be driven by an external CPU means that it can be used by more than one CPU, just as the CPU is produced to use more than one specialized circuit. If you were going to do it anyway, a problem with using the 6502 for it is economies of scope ... since the 6502 instruction set is not well suited for compiled C software, a lot of things have to be built from scratch that wouldn't have to be built from scratch if you used a low-power ARM architecture, and accept the larger mask footprint as the tradeoff for the much greater toolchain support base. And if you were going to do it ANYWAY, and build your own toolchain, then a stack machine would give you an even smaller transistor footprint with more MIPS than a 6502 of the same speed.
  11. Aren't economies of scale great? That's lower than the Q25 Mouser price of a 10ns PDIP MAX232's. With +/-12V available, as simple transistor based circuit would still be cheaper, but that's cheap enough it's not going to be noticeable.
  12. That is a possible interpretation. It does, however, refer to them as distinct items controlled by distinct circuits, so the two 7bit registers / extra address bit reading fits the language most closely. So I did a search, and found this in the VOPM Unofficial User Guide: So it's an extra address bit.
  13. It specifies that the individual piece of information (datum, "data" is its plural) is the 7bits and the high bit distinguishes between the two, and it refers to a PMD controlled item and an AMD controlled item, so yes, going by the language, there are two internal 7bit registers controlling those two functions and they are accessed via a common register address.
  14. I wasn't talking about the Altairduino, I was talking about the RS-232C to Ethernet box. The spec range of RS-232C is +3V<Logic0<+15V and -15V<Logic1<-3V, so if it's a direct connection, it would tolerate a very simple level conversion circuit.
  15. It bears keeping in mind that it's not unusual for standard government contracts to give preference to parts that are available from more than one supplier, so it is possible that a different provider as a second source of a compatible part can be a useful step to land a large government order. In that case, rather, "hey, why are you selling the customized design I ordered from you?" it can be, "c'mon, how soon am I going to be able to show that you are also selling the customized design I ordered from you?"
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