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Everything posted by BruceMcF

  1. The question is what you are aiming for with the hash. A hash that AIMS to avoid collisions, so collisions are a special case, is one approach, another is to just accelerate things compared to a sorted linked list or binary tree by having more but substantially smaller linked lists or trees, so that they do not get bogged down to the same extent as the wordspace grows. Then something as simple as the bottom four bits of the XOR of the bytes in the name may serve well.
  2. In the Forth's that stored 3 characters (eg, the original FIG Forths), they dealt with collisions by the first one defined was the one stored in the dictionary, "good grief, keep track of what you are doing, you idjit" ... similar to CMB Basic variable names except different length names with the same first three letters were also distinct ... in ANS Forth and successors, some implementations use hashing to speed up dictionary searches, but the entire name is stored.
  3. Though it seems pretty clear that we are going to be in the 65xx subset, unless a we get a 3rd party 65c816 daughterboard.
  4. There is no need to multiplex if you want to run the 65C816 inside the 16bit address space, which is perfectly possible. You have to add a pull up resister on a pin that is a rarely used clock output on the 65C02 and is an abort input on the 65C816, so it doesn't float. However, at the moment, it seems more likely that that is going to be on a 3rd party socket daughterboard.
  5. What @SlithyMatt said ... this isn't the scale for licensing out. And independent of selling a batch of systems to a foreign vendor, it's premature to work out whether it makes sense to have a quantity price break ... first the crowdfunding has to be launched, then it has to succeed, then the first systems have to be shipped, and then the market has to be tested to see if it will support ongoing production. It's a bit like planning on how to spend your Kentucky Derby winnings before the colt has been born.
  6. Yes, when you get past what the speed of the ROM supports, you either need to have clock-halving built into accessing the ROM memory window or else shadowing, either of which would complicate the design. I'm not a hardware hand, but I recall 8MHz being described as near the top of the comfortable access speed for the FlashROM for a 65xx type bus. And remember that the CX16p is the system reference design ... having the CX16p and CX16c with different top operating speeds would unnecessarily fragment the software base for what is already still a niche hobbyist system ... even if we hope it develops into a relatively big niche as far as hobbyist systems go.
  7. The design target was to run on original VGA, and original VGA was a 4:3 ratio display, not a 16:9 ratio display. Indeed, that was a secondary strike against the original FPGA video chip design, though the primary strikes were device contention between 6502 bus access and the J1 coprocessor and the lack of a true bitmap mode. Indeed, you can easily do a 640x360 display by just setting black bars at the top and bottom, and if shown on a TV with all the display options, it would fit. And 640x480 is pixel perfect on a 1440p display if you adjust the display width correctly.
  8. Actually, it can more convenient if Layer 1 is the PETSCII layer, since then menus and otherwise "pop-ups" can have the pretty PETSCII drawing characters, while the underlying "page" on layer 0 can be selectable between ISO and PETSCII.
  9. And the price point is just one part of it. It's an 8bit system with an 8bit processor driving an 8bit data bus. What would be the point of 24bit color support,for 1280x1024? How effectively could the 65c02 support it? 640x480 has a very real point: it allows 80 column text mode. Once that is hit (as some if not all 8bit systems did), the question becomes WHY raise the cost of the system with the next tier up FPGA in both number of available slices and available built in SRAM? There's always "more" to be hit in terms of resolution, which is why they are now pushing consumers to "upgrade" to 4K TVs. To paraphrase Jurassic Park, "your computer scientists were so busy trying to find out how to do it, they forgot to ask WHETHER they should do it."
  10. Is RAM built into an FPGA actually all that cheap? Did you price the families of FPGA with built in SRAM before making the claim? It's pretty central to the row buffer design that the SRAM the VERA is accessing is dual port asynchronous memory that VERA can access while running at 50MHz internally. Otherwise you lose a lot of your sprite per row capability.
  11. However, it remains highly infrequent ~ the most common frequency would be 0 ~ that there are 126 calls in a row between branches or literals, so just clearing a count when compiling a branch or a literal and incrementing it when compiling anything else, and inserting PGFIX if the increment passes 127 would suffice. It would almost never be triggered, and if triggered would rarely actually be needed, but the first means that the runtime penalty of the second is negligible. As far as the overhead of a Y indexed stack, the system efficiencies of not having return addresses and operands intermingled on the same single stack more than compensates for that.
  12. No, I didn't. WHILE/WEND and REPEAT/UNTIL loops are less flexible than CBM/QBasic Basic DO LOOP, and even there GOTO is stll needed for some loop structures. Making the tests orthogonal to the loop fixes that issue. BEGIN-BLOCK operation test operation END-BLOCK is the most generic loop structure, since it intrinsically provides: BEGIN-BLOCK test operation END-BLOCK BEGIN-BLOCK operation test END-BLOCK ... as the QBASIC DO [UNTIL/WHILE] ... LOOP [UNTIL/WHILE] loops do, and if done correctly, it can also provide: BEGIN-BLOCK operation1 test1 operation2 test2 operation3 END-BLOCK ... which is handy for a range of string processing loops ... test for condition, and test for end of string. The optimization referred to is that in the interpreter version, LOOP keywords can be chained together, (token $priorloopaddress) typically making finding the first loop following a failing test substantially faster than a BASIC GOTO that searches sequentially for the line. DO / LOOP can use the FOR/NEXT stack, by relying on an impossible variable reference address, such as $0000.
  13. But as described, your only control structures are IF/THEN and floating point FOR ... NEXT, since in Basic V2, there ARE no keywords for any other control structures, they are all built with IF/THEN and GOTO, and you say there are no GOTO. If you want it more Basickey, DO: ... :UNTIL(): ... :LOOP DO: ... :WHILE(): ... :LOOP
  14. That's what the expansion hoards are for. Seems like a 6551 expansion board would be pretty straightforward.
  15. Disk space will certainly not be precious at the scale of keywords of eight bytes or less. And of course, once they've been tokenized, the original size of the text string won't matter any more. Also note that in the above, the ":", " (" and ")" are implied in the parsing, so the space overhead over obscure pairs of punctuation characters is a net 20 bytes.
  16. Note, I would not expect a CX16c to come with expandable RAM, but since a 1MB SRam might be available in surface mount, I would be OK with the LowRam coming from the top 40K of a 1MB SRAM and 123 segments of High RAM available.
  17. One advantage is that the keywords for those are already reserved, and new keywords are by far the easiest type of extension to make to an MS 6502 Basic V2 based system.
  18. Yeah, US prices are pre-consumption-tax ("sales tax" in the US rather than VAT or GST, which can not only vary by state but can also vary by county or city), so short of a friend visiting the US able to bring something in under their duty limit, there's no legal getting around bumping up the price by your country's VAT rate. But having a reseller in the EU could well get shipping costs down dramatically. While it seems unlikely that the unit will be selling at a margin to allow a reseller to get THEIR operating margin from the difference between a wholesale and retail price, there IS a saving in handling costs in shipping off a batch order, so maybe there can be a modest discount to an EU reseller buying a batch, to reduce the difference between US retail price and EU retail price. The UK is even trickier, because they require foreign sellers to collect UK customs and other taxes FOR the UK, and there is a charge for registering to be a UK tax collector on top of that, making it uneconomic for many small volume producers to sell into the UK. The best chance for a UK resident wanting to get their hands on some retro gear from the US might be a quick trip to Belfast, which is inside the EU customs union.
  19. Yes, it had a NEC V30, which was an 8MHz 8086 chip, so roughly equivalent to an XT, but slightly faster due to some instructions running in fewer clock cycles. For running WordPerfect 5.1 for DOS to write my dissertation, it was quite smooth, as well as running AWK scripts in a DOS port of an open source Linux AWK. For running my maximum entropy estimator, written in C, it was SLOW, and glacially slow when running in debug mode, but if it hadn't been for the PowerC with integrated debugger, I doubt I would have ever finished that program. Really, the only part of it I am nostalgic for as I type on my hand me down and now "old" SONY Viao laptop is the keyboard. It wasn't a sweet Cherry mechanical switch keyboard, but it was full size, full travel, with all of the keys in the right places. So the primary reason I wish I still had it (it died in a flooding of my US storage unit during my decade in Australia) is that the V30 also has a direct 8080 opcode emulation mode, so it can run CP/M directly at 8Mhz, which is otherwise quite a trick for an IBM-XT class system.
  20. Sure you can, but then in the eyes of many, then it's just another ATMel Micro project. The appeal of using the 6551 for the reference design is that it's an ASIC in production. Also, if you want to emulate a 6551, you need to run it at a fairly high clock speed to read and write the registers in a single 65C02 clock cycle at 8MHz without the use of the RDY line. That's one difference between this project and doing a similar chip emulation on a C64 system ... for any given microcontroller clock speed, you have 1/8th the clock cycles to present a register data that is being read in the current phi2 low phase (reads are normally the bottleneck if the microcontroller allows you to set up the data lines with an internal buffer).
  21. The pointer in JMP (COLD,X) pointer is updated with every branch or call to a high level routine ... and if there is any serious issue of having 128 consecutive primitives, a check on number of primitives compiled and an "update pointer" primitive can eliminate that constraint, though a word that has 128 consecutive primitives is a symptom of a deeper failure to factor code properly. As far as stacks, the 65C02 has an implicit S register stack, as many explicit addr,X or addr,Y stacks as there are pages of RAM, (zp),Y stacks for stacks of data frames. Anyone who faces a constraint because they have boxed themselves into only using a single stack only has themself to blame.
  22. I can see Basic keyword's for operations, but Basic keywords for control structures is killing a lot of opportunity for optimization. IF: ... :ELSE: ... :THEN BEGIN: ... :UNTIL() BEGIN: ... :WHILE(): ... :REPEAT FOR(): ... :NEXT()
  23. But the point was made about Basic 7, which has it's memory banking operation directly reflecting Commodore 128 memory banking, its music keywords directly reflecting the SID chip and it's graphical keywords assuming the available C128 graphical displays. The last code delivery CBM took from MS was MS Basic v2 ... CBM Basic 3.5 and 7'were in-house extensions.
  24. Yeah, I got that one basically BECAUSE it wasn't a big hit in the market, being less portable than a laptop and less powerful than a desktop with a hard drive: I bought it from an electronics discounter who seems to have got stock being liquidated. For me, it was a cheap PC cheaper than a desktop + monitor would have been. The ability to be car-mobile with a cigarette lighter plug was a pure bonus.
  25. Yeah, it's got to be do-able, WDC sells FPGA cores of their VIA's.
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