Jump to content


  • Content Count

  • Joined

  • Last visited

  • Days Won


Everything posted by SlithyMatt

  1. That's a general issue with the emulator mouse support. Nothing you can do about it from inside the X16 code. What I find helps is to drag the mouse across the screen until it stops as the edge, then bring it back across all the way to the other side, then back to the middle. From there, do the same in the vertical directions, and the mouse should be synched with emulator.
  2. It's a bit premature to bother with that. The final code is likely to be very different by the time of release. Try to use the Kernal API.
  3. Sounds like R0 is not getting recognized as an 8-bit value or there's a bug in cc65. Did you try just STA ($02),y? For zero page addresses, you may need to have separate identifiers for zero page address values and usable pointers.
  4. Seriously, you can make this one byte shorter by substituting a BNE or BRA for the JMP.
  5. Y gets set from your feeling of self-importance. X is loaded with zero just to publicly emasculate it.
  6. That's correct. You'll want to change the tileset address for layer 1.
  7. I think he may have been referring to a complete X16 system-on-a-chip, not just the VERA.
  8. It is. That's what I do in most of my programs, and it works just fine as long as I have the bank set back to 4 before the RTS that should take us back to BASIC. However, certain RAM and VRAM states may make that difficult, so there may need to be other resetting needed.
  9. I bet @Frank van den Hoef wouldn't mind a fat royalty check to have WDC convert VERA to an ASIC, but the likelihood of that check coming is practically nil.
  10. It wouldn't be too bad, as the X16 has so much more RAM and CPU cycles to spare compared to the C64 or the NES, which needed hardware support to do that effectively. Ultimately, you'll still end up ahead, especially if you do the envelope handling programmatically, rather than timed hard-coded changes to the PSG registers, which could take up a lot of RAM compared to an envelope spec.
  11. That would be correct. The FIFO loading can be intensive, but only during that burst of loading. You can load balance by doing shorter bursts more often, which would also prevent you from wasting cycles on FIFO'd sample data that is flushed before it plays.
  12. NTSC video from composite or S-Video will both be interlaced, meaning that 640x480 at 60Hz is not going to really work without progressive scan. 320x240 should look ok after interlacing.
  13. Not really, it's more memory intensive. Samples take up a huge amount of memory, relatively speaking, compared to PSG or FM settings. But once you have a sample in memory, you don't have to service the PCM FIFO very often, and even then it doesn't take very long. It actually requires less CPU intervention than PSG or FM.
  14. Lesson 4: Arithmetic and Logic
  15. They are custom made for their custom LCD displays, so not something designed to work on a standard TV or monitor. Generally, they are extremely slow frame rates, like 5 fps, so not good for gaming - various attempts at Doom and Tetris notwithstanding.
  16. My guess is that their Windows control panel requires the DOS TSR to be resident in RAM to work. A pretty big kluge, but it probably works!
  17. I think this may have been a TSR program for a particular sound card that let you control how sound was going out to the speakers, maybe a fade and EQ panel that could pop up?
  18. As @Perifractic would say, "DEWIT!"
  19. Welcome! I love to see more demos!
  20. Very cool! I wonder if you could get beige sticker stock to make it match better?
  21. You basically have two other options, both orders of magnitude more expensive: ASIC (but that expense can be mitigated by volume) or discrete logic (which will not only be much more expensive, but require a large expansion card, taking up one of the slots by necessity)
  • Create New...

Important Information

Please review our Terms of Use