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Everything posted by Andre

  1. The REL file handling in CBM DOS is fairly buggy. You have to work around a number of special conditions. (edit: see e.g. the test suite https://github.com/fachat/XD2031/tree/master/fwtests/relfiles ) But maybe you want to create a REL file driver for the high RAM?
  2. That's not correct. A command always starts with a command, in case of copying a file, it's "COPY" (or "C" for short). So it should be "C:New_file=Original_file", or even concatenating multiple files: "C:new_file=old_file1,old_file2,old_file3"
  3. Sorry for the late reply. I'm totally with @BruceMcF about the handshake mode of the CA1/CA2 pins of the VIA. Pls see the VIA datasheet for the details how it works. On the pin assignment I am not clear what the difference is between PB4/ACK and CA1 (or CA2?) Is ACK and output or input? On SPI - you can have an easy SPI interface with the VIA using a single ser-2-par shift register, and XORs for other modes. See here http://www.6502.org/users/andre/csa/spi/index.html
  4. What about SSOP? It's not through-hole but better to solder than TQFP. E.g. this one https://datasheets.maximintegrated.com/en/ds/MAX3107.pdf (Note: haven't used it myself, just quickly googled it) Or this one seems to be available in 14 pin DIP: https://docs.rs-online.com/ec74/0900766b80811942.pdf
  5. Just a simple addition: (5) the IFR with the interrupt flags - and thus edge detection - can be read even when the interrupts themselves are disabled. CPU interrupts are only enabled if the IFR register bit _AND_ the corresponding IER (interrupt enable register) are set. Pls. have a look at the VIA datasheet for more details.
  6. yes I have. That's the back side indeed. (but if you want to have a look how it could work, look at my 6502 USB driver linked above, via the PET userport SPI)
  7. In fact _my_ dream computer nowadays would just have a number of SPI-based module ports, and no parallel bus connector anymore. You could plug in SPI modules for serial, USB, memory, Ethernet, whatever you dream of. And btw run your main computer on any fast speed as you like, as there is no external bus to take care of.
  8. PS/2 ????? Do you have so many junk old keyboards lying around? I've thrown away all my PS/2 already, as it's too young for 8-bit and to old for modern PCs.... Instead I taught my Commodores to use USB keyboards
  9. Now you don't tell me that if you move the mouse while loading a file breaks the IEC bus (as this is big-banged and allergic to NMI)? I'm not opposed to SPI, or SPI UART, in fact I think an SPI interface with potentially multiple devices on it is a nice thing - given that SPI is not bit-banged but using a real shift register. I've done USB-over-SPI on the Commodore PET userport using the VIA shift register, and can use a USB mouse on the PET just fine. But it required a) VIA shift out via SR, and b) a 74 series TTL serial-to-parallel shift register to shift in the data at the same time as SPI does. And it VIA can only handle SPI mode 3 "out of the box". See my solution here: http://www.6502.org/users/andre/csa/spi/index.html Edit: the userport USB is here: http://www.6502.org/users/andre/cbmhw/cbmusb/index.html
  10. Absolutely agree. A couple of cycles is ok, but if it gets more, the driver should back up and e.g. enable interrupt, if only to be able to break out of the wait loop and not maybe hang indefinitely. (does X16 have an NMI key?).
  11. From the view of an operating system programmer, busy waiting / polling is wasted CPU. I would want something that does automatic handshaking, and provides interrupts when data is available or buffers are empty. That relates to VIA handshaking mode, or an UART with its FIFOs. Even the Commodore serial bus wanted to use hardware features to avoid bit-banging. It only became a total failure just because the VIA shift register they planned to use was buggy (which isn't in the WDC VIA anymore as far as I know). If we're building a "dream" computer, we should avoid such decisions. Rather have an expansion slot where e.g. a UART can be placed.
  12. Hardcode zeropage locations? I hope you're using some modern tools like relocatable binaries?
  13. You know that the VIA has "handshake mode" on the PA? This is allowing to automatically bump the CA2 line when reading or writing PA, to signal the transfer to an external device. See the VIA datasheet for more details. This is very handy in such situations. Edit: also, PA and PB can be "latched" on input on positive or negative edge of CA1/CB1 respectively.
  14. The X16 remaps an 8k window of RAM and a 16k window of ROM in the upper area. Remapping e.g. the lowest part could work similarly even without an MMU. But I understand, someone has to implement it.
  15. That's what I noticed. So has this been discussed as an option? If so, what was the rationale to exclude this feature?
  16. Sorry I'm late to the game, I am wondering why the zeropage and/or stack cannot be remapped to a different memory location (except I have overseen something) like e.g. in the C128. I would make things like transient programs, or even multitasking so much easier, especially as the X16 is supposed to be 8 times faster than the old CBMs. Thanks
  17. Not only that. It is also using the NMI, that is, in general, incompatible with precise IEC bus timing.
  18. http://www.6502.org/users/andre/icaphw/c64ser.html Baseline, public design to integrate a UART into a 6502 system.
  19. There are TCP/IP drivers available for the 6502. GeckOS has one (assembler), and uIP (in C) is working even better.
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