So ... I've been watching with interest, but not contributing because I didn't see anything I needed to say. I do now.
I think the function of the 64/128 REU's memory transfer function is under-appreciated. It's like a budget blitter chip. Your memory design has 2M of memory in an 8k bottleneck. Something along the lines of the REU that could:
- memory <--> bank
- bank <--> vera
- memory <--> vera
might make things massively more functional and enable a slate of games that wouldn't be possible otherwise. One flaw in the single 8k bank is that you can't effectively have segmented code and segmented data in a program ---- you have to choose one.
I looked at REU implementation for the MiSTeR FPGA project --- it's not a lot of FPGA code (or space) to do that.
Anyways... just a comment.