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raygard

Speed of later models

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As the circuitry gets smaller in the future models, will the speed go up, and if so, by how much?

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I would say it's just too soon to say given the current design is still being ratified but I would expect the current X16 models (P, C, and E) will all be running 8MHz and wouldn't expect there to be any changes at this point.

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I would agree that we do not expect to change the speed of the product. In some cases features may be taken away as the board gets simpler, so it would be contradictory to also give it a speed improvement for less money.


Perifractic, X16 Visual Designer
http://youtube.com/perifractic

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Note, I would not expect a CX16c to come with expandable RAM, but since a 1MB SRam might be available in surface mount, I would be OK with the LowRam coming from the top 40K of a 1MB SRAM and 123 segments of High RAM available.

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9 hours ago, raygard said:

If we were so inclined -- just from a technical standpoint -- how fast could it go?

Western Design Center (WDC) has been rating their MCU's and MPU's at 14 MHz for years now, and testing them at 20 MHz.  ASIC's based upon 65C02 (and variant) cores have been reported by WDC to run at speeds of 200 MHz, but in those cases most of the supporting chips (memory, glue logic, etc.) are no doubt physically integrated into the same chip.  People have overclocked recent stock 65C02 and 65C816 MPU's at speeds of up to 29.5 MHz successfully.  This doesn't mean that you could necessarily run a Commander X16 at that speed - the rest of the system, including bus, glue logic, other chips, etc. would also need to be capable and designed in such a way as to accomplish that.  Reading threads over at 6502.org I see a lot of people building 6502 (and variant) based computers where they experiment with clock speed, and often find they need to replace components or completely redesign to maintain stable operation at some point.  Sometimes that speed is less than the MPU's rated speed, sometimes they can get well above it - it all depends upon the overall system design.   

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10 hours ago, raygard said:

If we were so inclined -- just from a technical standpoint -- how fast could it go?

Additionally, the X16 team was targeting 8MHz because that was the fastest they'd been able to clock the chip on the board.

So - just from a technical standpoint - it will probably go about as fast as they ship it.

Edited by StephenHorn

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Yes, when you get past what the speed of the ROM supports, you either need to have clock-halving built into accessing the ROM memory window or else shadowing, either of which would complicate the design. I'm not a hardware hand, but I recall 8MHz being described as near the top of the comfortable access speed for the FlashROM for a 65xx type bus.

And remember that the CX16p is the system reference design ... having the CX16p and CX16c with different top operating speeds would unnecessarily fragment the software base for what is already still a niche hobbyist system ... even if we hope it develops into a relatively big niche as far as hobbyist systems go.

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31 minutes ago, BruceMcF said:

Yes, when you get past what the speed of the ROM supports, you either need to have clock-halving built into accessing the ROM memory window or else shadowing, either of which would complicate the design. I'm not a hardware hand, but I recall 8MHz being described as near the top of the comfortable access speed for the FlashROM for a 65xx type bus.

And remember that the CX16p is the system reference design ... having the CX16p and CX16c with different top operating speeds would unnecessarily fragment the software base for what is already still a niche hobbyist system ... even if we hope it develops into a relatively big niche as far as hobbyist systems go.

 

Maximum speed for the ROM chips is one of the common first stumbling blocks for increasing clock speed.  That can be dealt with by clock stretching, wait stating, etc. but that adds some extra complexity and some propagation delays with the required "glue logic."  Speed of other glue logic, or of supporting chips (VIA, UART, etc.) are usually the next stumbling blocks.    I can readily understand why the Commander X16 crew stopped at 8 MHz, though I wish they'd managed to incorporate a 65C816 instead of a 65C02 - I understand not wanting to mess with the multiplexed bank/data lines, especially since WDC's reference design for doing so has known problems.

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8 hours ago, Sean said:

 

Maximum speed for the ROM chips is one of the common first stumbling blocks for increasing clock speed.  That can be dealt with by clock stretching, wait stating, etc. but that adds some extra complexity and some propagation delays with the required "glue logic."  Speed of other glue logic, or of supporting chips (VIA, UART, etc.) are usually the next stumbling blocks.    I can readily understand why the Commander X16 crew stopped at 8 MHz, though I wish they'd managed to incorporate a 65C816 instead of a 65C02 - I understand not wanting to mess with the multiplexed bank/data lines, especially since WDC's reference design for doing so has known problems.

There is no need to multiplex if you want to run the 65C816 inside the 16bit address space, which is perfectly possible. You have to add a pull up resister on a pin that is a rarely used clock output on the 65C02 and is an abort input on the 65C816, so it doesn't float. However, at the moment, it seems more likely that that is going to be on a 3rd party socket daughterboard.

Edited by BruceMcF

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Indeed.  The 8 Mhz limitation is due to various components on the board such as ROM, the sound chip, the Vera, etc.   In fact, we only have it working stable at 4 Mhz at the moment on the latest rev of the proto-board.  But, with a few minor changes we still fully expect to get it back up to 8 Mhz and stable.  

Having said that, stage 2 and stage 3 do present the possibility to go faster.  Specifically stage 3, which is all inside a single FPGA.  We have a prototype of that which runs at 14 mhz and seems stable.  But, as far as the DIP style board, which serves as the basis for the whole computer architecture, 8 Mhz will likely be all you will ever see.

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46 minutes ago, The 8-Bit Guy said:

stage 3, which is all inside a single FPGA.  We have a prototype of that which runs at 14 mhz and seems stable

Oh my.  That. Sounds. Awesome. I love and hate you right now. 🙂

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2 hours ago, The 8-Bit Guy said:

Indeed.  The 8 Mhz limitation is due to various components on the board such as ROM, the sound chip, the Vera, etc.   In fact, we only have it working stable at 4 Mhz at the moment on the latest rev of the proto-board.  But, with a few minor changes we still fully expect to get it back up to 8 Mhz and stable.  

Having said that, stage 2 and stage 3 do present the possibility to go faster.  Specifically stage 3, which is all inside a single FPGA.  We have a prototype of that which runs at 14 mhz and seems stable.  But, as far as the DIP style board, which serves as the basis for the whole computer architecture, 8 Mhz will likely be all you will ever see.

Aha, hence "enhanced", a "turbo" mode, a la the original IBM PC and the IBM XT.

But it's phase 2 I have my eye on, and I'm more hoping that it has the real sound chip  than worrying about it's clock speed. I can buy heaps of Chinese portable game consoles with much faster clock speeds than the CX16p for well under $100 ... but I am not interested in doing much programming on them.

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Posted (edited)
4 hours ago, The 8-Bit Guy said:

Indeed.  The 8 Mhz limitation is due to various components on the board such as ROM, the sound chip, the Vera, etc.   In fact, we only have it working stable at 4 Mhz at the moment on the latest rev of the proto-board.  But, with a few minor changes we still fully expect to get it back up to 8 Mhz and stable.  

Having said that, stage 2 and stage 3 do present the possibility to go faster.  Specifically stage 3, which is all inside a single FPGA.  We have a prototype of that which runs at 14 mhz and seems stable.  But, as far as the DIP style board, which serves as the basis for the whole computer architecture, 8 Mhz will likely be all you will ever see.

I should mention that Gideon has managed to get the Ultimate 64 running at 48MHz. So it's definitely possible to run the 6502 at that speed; although I'm not sure precisely how he manages the CIAs and other forms of I/O, though.

If the U64 only had an 80-column output....

 

Edited by TomXP411

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5 hours ago, TomXP411 said:

I should mention that Gideon has managed to get the Ultimate 64 running at 48MHz. So it's definitely possible to run the 6502 at that speed; although I'm not sure precisely how he manages the CIAs and other forms of I/O, though.

If the U64 only had an 80-column output....

 

Looking at reviews and photos on the Ultimate 64, it looks to me like the U64 eschews physical instances of the typical supporting 65XX chips.  Presumably any I/O support is part of the FPGA.  There are sockets for physical SID chips, but I suppose they can use variable clock speed to interface with those if installed.  From what I've read on 6502.org, it gets a lot easier to achieve stable faster clock speeds when most of the system is on a single chip.  

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Not had much input into these things but it seems that at the very least the phase 2 and 3 versions should have the same speed (if not all of them). If you don't you end up with the issue that the original systems had which is that when making software you will always end up aiming for the lowest common denominator. Even worst if someone writes software that is CPU speed dependent (I guess you would need a Turbo button :))

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1 hour ago, Cunnah said:

Not had much input into these things but it seems that at the very least the phase 2 and 3 versions should have the same speed (if not all of them). If you don't you end up with the issue that the original systems had which is that when making software you will always end up aiming for the lowest common denominator. Even worst if someone writes software that is CPU speed dependent (I guess you would need a Turbo button :))

The present prototype board is wired to be selectable between 2, 4 and 8MHz ... that's what the reference to only booting it up stable at 4MHz at the present is. So, eg, a jumper to select between 8MHz and 12MHz in phase 3 (CX16"e") shouldn't not be TOO difficult.

 

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2 hours ago, BruceMcF said:

The present prototype board is wired to be selectable between 2, 4 and 8MHz ... that's what the reference to only booting it up stable at 4MHz at the present is. So, eg, a jumper to select between 8MHz and 12MHz in phase 3 (CX16"e") shouldn't not be TOO difficult.

 

That makes sense (and I recall that being the case from the previous videos) I guess it needs to be locked down for the later revisions if the intention is to avoid devices competing with each other and a split software base (or more likely an unused potential)

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15 hours ago, Cunnah said:

That makes sense (and I recall that being the case from the previous videos) I guess it needs to be locked down for the later revisions if the intention is to avoid devices competing with each other and a split software base (or more likely an unused potential)

Well, hopefully the CX16P and CX16C have the same hardware constraints on their ASIC chip timings, which would imply the same speed constraint. The only one where that hardware constraint would not be the same would be the CX16E. So a common speed for all three and a single "turbo" mode option for the CX16E is what makes sense for me.

Mind, it's not my call, and I'm not worried about the design team making a real blunder, so I'm not going to fret about it.

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