Jump to content
CreativityTheEmotion

What is the Commander X8?

Recommended Posts

53 minutes ago, BruceMcF said:

Whether VERA ... or indeed any Video processor that meets the target for an "8bit dream machine" ... somehow stops the system "feeling like" an 8bit system because video systems in 8bit and 16bit systems were not big discrete steps but a continuum of different capabilities, so "an upgraded 8bit style video system" will necessarily overlap with some of the specs and features of 16bit systems back in the day: "... it was losing its '8 bit feel' and spec wise was competitive with 16/32 bit computers of the day."

The only clear divide I can see in that continuum are the systems that started the process of offloading video processing chores from the CPU, and Vera is on the 8bit side of that divide.

Hardware acceleration doesn't define the divide for me because PCs with SVGA cards that had no hardware acceleration would soon outperform the 68K based home computers that did and subsume the games market that was the primary driver of those devices. Also, the MOS 8563 VDC used in the C-128 could blit memory blocks in video ram and it was definitely an 8 bit system. In 8 bit systems, we had to work around some sort of limitation caused by real world constraints and it was the results of those that defined the 8 bit feel.

All of this ignores that what we're calling a video chip is also the most capable audio chip on the CX16 that by some measures blows away the audio capabilities of 16/32 bit home computers of the day - plus it has the high speed mass storage controller. The primary reason for my calling the 8 bit experience into question was that all of these functions were being consolidated into a single "chip":

On 3/15/2021 at 12:17 PM, Wavicle said:

consolidating functionality to VERA made the project look like an over-engineered 8 bit controller for an FPGA device; it was losing its "8 bit feel" and spec wise was competitive with 16/32 bit computers of the day.

An FPGA video solution was a practical necessity of the CX16; I don't see much argument on that front. The first version of the VERA shown in "Building my Dream Computer - Part 2" video was essentially just an equivalent to a discrete video chip. It had no ports and served one function. It's the subsequent use of it as a "kitchen sink" where new features - and even ports - were added that feels off to me. It has effectively become a required expansion card.

Share this post


Link to post
Share on other sites

The features that were added to VERA over time were all added for specific reasons. The PSG (and likely the PCM) was added because although it is possible to obtain sound chips with similar features, they are not entirely reliable. Therefore, each one would have to be tested before being used. I believe the team added sound functionality to VERA to prevent having to test another chip in addition to the YM2151. As for the SD card controller, I would not be surprised if most of the other SD card solutions available were more powerful than the rest of the system combined. The main purpose of the VERA is to supply functionality that would be difficult or impractical to supply using only off-the-shelf parts.

Share this post


Link to post
Share on other sites
12 hours ago, Wavicle said:

All of this ignores that what we're calling a video chip is also the most capable audio chip on the CX16 that by some measures blows away the audio capabilities of 16/32 bit home computers of the day - plus it has the high speed mass storage controller. The primary reason for my calling the 8 bit experience into question was that all of these functions were being consolidated into a single "chip":

An FPGA video solution was a practical necessity of the CX16; I don't see much argument on that front. The first version of the VERA shown in "Building my Dream Computer - Part 2" video was essentially just an equivalent to a discrete video chip. It had no ports and served one function. It's the subsequent use of it as a "kitchen sink" where new features - and even ports - were added that feels off to me. It has effectively become a required expansion card.

Well, I'll admit I'm partial to the argument that it feels uncomfortable for PSG functions to be mapped to VRAM addresses. There are some conveniences since we can take advantage of auto-incremented addresses in the data channels for applying changes in bulk, but it's still "odd".

But I respect that this ultimately derives from a cost-reduction and hardware-simplification strategy that avoids having to place a second FPGA on the board. Maybe there's an argument to be made over whether the "nominal purity" of the vision is worth the extra monetary and design cost of another FPGA, but I think there's also an argument to be made that if FPGAs are unavoidable, maybe it's better to try to consolidate them now and avoid inflating the price of the unit.

Share this post


Link to post
Share on other sites
5 hours ago, Elektron72 said:

The features that were added to VERA over time were all added for specific reasons. The PSG (and likely the PCM) was added because although it is possible to obtain sound chips with similar features, they are not entirely reliable. Therefore, each one would have to be tested before being used. I believe the team added sound functionality to VERA to prevent having to test another chip in addition to the YM2151.

Why is another chip in addition to the YM2151 necessary? According to the FAQ the final decision has not yet been made, but it seems like the decision now is between VERA alone or VERA+YM2151.

5 hours ago, Elektron72 said:

As for the SD card controller, I would not be surprised if most of the other SD card solutions available were more powerful than the rest of the system combined.

Check the history. An early concept was an onboard SD2IEC adapter.

5 hours ago, Elektron72 said:

The main purpose of the VERA is to supply functionality that would be difficult or impractical to supply using only off-the-shelf parts.

That may be what it has become; that was not the original vision.

Share this post


Link to post
Share on other sites
Posted (edited)
On 3/19/2021 at 4:00 AM, Wavicle said:

Why is another chip in addition to the YM2151 necessary? According to the FAQ the final decision has not yet been made, but it seems like the decision now is between VERA alone or VERA+YM2151.

Check the history. An early concept was an onboard SD2IEC adapter.

I think that first one is more according to the FAQ at the time of writing that section of the FAQ ... at the time it first had that language, the SAA1099 was still in the design mix. AFAIR, the PSG was part of the original design target of the Vera designer, and the question of why the SAA1099 was needed was raised the first time the PSG capabilities were described.

But as @Lorin Millsap alludes to, the SAA1099 is one of those chips with a PIC-ish multiplexed data and register address buses, and integrating that onto a 65xx bus is an additional complication to bringing up the board. And it's different timings from the YM2151 ... CS can be synchronous to A0, but /WR has to be at least 30ns after /CS. Given that the designer of Vera was including the PSG in any event, relying on the PSG for initial testing of the working of the audio output rather than the SAA1099 does seem like it has fewer ways to fail.

On the second point, IMV putting a microcontroller on the board to emulate the IEC protocol for accessing an SD card would have been LESS like an actual classic 8bit computer than having a simple SPI port for the 65C02 to access an SD card over SPI protocol, and more like emulating a classic 8bit computer peripheral ... in addition to being substantially more expensive ... so I see that as more a step toward the original vision than a step away. After all, SPI is just one MOSI line away from the NES/SNES controller interface.

And the "setting it up using VRAM locations" isn't an issue, it's direct reads to two direct memory mapped I/O addresses.

Edited by BruceMcF

Share this post


Link to post
Share on other sites
10 minutes ago, BruceMcF said:

I think that first one is more according to the FAQ at the time of writing that section of the FAQ ... at the time it first had that language, the SAA1099 was still in the design mix. AFAIR, the PSG was part of the original design target of the Vera designer, and the question of why the SAA1099 was needed was raised the first time the PSG capabilities were described.

But as @Lorin Millsap alludes to, the SAA1099 is one of those chips with a PIC-ish multiplexed data and register address buses, and integrating that onto a 65xx bus is an additional complication to bringing up the board. And it's different timings from the YM2151 ... CS can be synchronous to A0, but /WR has to be at least 30ns after /CS. Given that the designer of Vera was including the PSG in any event, relying on the PSG for initial testing of the working of the audio output rather than the SAA1099 does seem like it has fewer ways to fail.

The first public mention of putting audio on VERA I'm aware of was at the tail end of the Building My Dream Computer - Part 2 video with the context "if either of [YM2151 or SAA1099] fail to work out, Frank has also said he could add some sound to the VERA chip that would give it an 8 channel sound system that would sound similar to the SID chip in the Commodore 64. So we just don't know where the sound will wind up."

Taking what was said in that video literally, audio on VERA:

  1. Was not intended as part of the original design
  2. Was raised as a possibility if something went wrong with the other options
  3. Was not an inevitability
27 minutes ago, BruceMcF said:

On the second point, IMV putting a microcontroller on the board to emulate the IEC protocol for accessing an SD card would have been LESS like an actual classic 8bit computer than having a simple SPI port for the 65C02 to access an SD card over SPI protocol, and more like emulating a classic 8bit computer peripheral ... in addition to being substantially more expensive ... so I see that as more a step toward the original vision than a step away. After all, SPI is just one MOSI line away from the NES/SNES controller interface.

I was stating what old versions of the vision said. I do not think calling the current interface a "simple SPI port" is accurate because the FPGA has a hard IP SPI controller block. The CPU isn't bit-banging the SPI interface; the only wire the CPU can directly affect is CS#.

(And arguing "SPI is just one MOSI line away from the NES/SNES controller interface" is bizarre. That pin is the difference between listening and communicating.)

Share this post


Link to post
Share on other sites
6 hours ago, Wavicle said:

The first public mention of putting audio on VERA I'm aware of was at the tail end of the Building My Dream Computer - Part 2 video with the context "if either of [YM2151 or SAA1099] fail to work out, Frank has also said he could add some sound to the VERA chip that would give it an 8 channel sound system that would sound similar to the SID chip in the Commodore 64. So we just don't know where the sound will wind up."

Taking what was said in that video literally, audio on VERA:

  1. Was not intended as part of the original design
  2. Was raised as a possibility if something went wrong with the other options
  3. Was not an inevitability

I was stating what old versions of the vision said. I do not think calling the current interface a "simple SPI port" is accurate because the FPGA has a hard IP SPI controller block. The CPU isn't bit-banging the SPI interface; the only wire the CPU can directly affect is CS#.

(And arguing "SPI is just one MOSI line away from the NES/SNES controller interface" is bizarre. That pin is the difference between listening and communicating.)

I'm just saying that in addition to those two videos, there were additional things stated back at that time on the Facebook group.

(1) Since I was reporting the mention at about that time that it came from what Frank wanted to do with Vera, that would imply that I did not claim "it was intended as part of the original design". (2) That may have been the understanding David had of it when he made the video, and (3) introducing a point to the discussion to contradict what hasn't been said.

OTOH, it is not like the PSG system is out of place among the various 8bit sound chips in the era, so those points seem like they are more for the pointless hand waving arguments about how far or close the reality is to what different people imagined a system would be from the earliest descriptions of the idea.

As far as SPI having to be bit banged to be 8bit ... if you stick to the phase and mode that is natural to the CIA, you can literally make an SPI port on the C64 User Port out of the serial shift registers on the C64 (and, ironically, the only reason both are available is the original MOS VIA's did not function correctly for using the serial shift register for the IEC protocol in the VIC-20), and the only reason you need both is that the CIA shift registers are single ended. But you do it in the normal way, same as an RS-232C serial port on a professional 8bit CP/M system, by writing data and control information into registers and letting the I/O chip do the serial, not by Tramgineering bit banging GPIO.

Heck, if the CIA had serial shift registers with a carry line, you would only need one of the serial shift register. Indeed, burst mode in the C128 with a 1571 and/or 1581 uses the hardware clocked serial shift register function of the CIA (even though if was for nought because the games market was locked on the install base of the C64+1541 drive).

Share this post


Link to post
Share on other sites
3 hours ago, BruceMcF said:

I'm just saying that in addition to those two videos, there were additional things stated back at that time on the Facebook group.

(1) Since I was reporting the mention at about that time that it came from what Frank wanted to do with Vera, that would imply that I did not claim "it was intended as part of the original design". (2) That may have been the understanding David had of it when he made the video, and (3) introducing a point to the discussion to contradict what hasn't been said.

OTOH, it is not like the PSG system is out of place among the various 8bit sound chips in the era, so those points seem like they are more for the pointless hand waving arguments about how far or close the reality is to what different people imagined a system would be from the earliest descriptions of the idea.

As far as SPI having to be bit banged to be 8bit ... if you stick to the phase and mode that is natural to the CIA, you can literally make an SPI port on the C64 User Port out of the serial shift registers on the C64 (and, ironically, the only reason both are available is the original MOS VIA's did not function correctly for using the serial shift register for the IEC protocol in the VIC-20), and the only reason you need both is that the CIA shift registers are single ended. But you do it in the normal way, same as an RS-232C serial port on a professional 8bit CP/M system, by writing data and control information into registers and letting the I/O chip do the serial, not by Tramgineering bit banging GPIO.

Heck, if the CIA had serial shift registers with a carry line, you would only need one of the serial shift register. Indeed, burst mode in the C128 with a 1571 and/or 1581 uses the hardware clocked serial shift register function of the CIA (even though if was for nought because the games market was locked on the install base of the C64+1541 drive).

Do you have a link to the conversation on the Facebook group? Earliest mention I could find is https://www.facebook.com/groups/CommanderX16/permalink/637566960327735 which came five months after the video.

(1) You wrote: "AFAIR, the PSG was part of the original design target of the Vera designer". That statement was being addressed by this point.

(2) It seems reasonable that this was David's understanding at that time because there had not been anything said to suggest otherwise. The timing of mentions I could find in the FB group are consistent with this. Again: do you have a link to something earlier that would square this?

(3) You wrote: "Given that the designer of Vera was including the PSG in any event". That statement was being addressed by this point. What do you think is being introduced that hasn't been said?

I never stated "the PSG system is out of place among the various 8bit sound chips in the era" or "SPI having to be bit banged to be 8bit".

Share this post


Link to post
Share on other sites
Posted (edited)
18 hours ago, Wavicle said:

I never stated "the PSG system is out of place among the various 8bit sound chips in the era" or "SPI having to be bit banged to be 8bit".

I was reading the objection, "The CPU isn't bit-banging the SPI interface; the only wire the CPU can directly affect is CS#." ... I didn't see what other relevance it was supposed to have that the SPI is being accessed like a normal I/O chip of the era rather than being bit banged. If an SPI interface was built out of a serial shift register with carry and glue logic, you'd have one register address where you read/write the data and another where you'd set the control settings.

The Commodore VIC-20 and then following it the C64 bit banged the IEC bus because they messed up the design of the VIA serial shift register option that was supposed to handle the hardware serial bus ... if that hadn't of been messed up, the IEC would have been substantially faster, and it would have been accessed in the same way that you are objecting to here ... the 6510 writing control set-up to an I/O register address and writing data to or reading data from a different I/O register address.

The TTL levels UART for the add-on serial interfaces was bit banged on the User Port because Jack Tramiel didn't want the cost of a serial chip in his VIC-20 or C64.

18 hours ago, Wavicle said:

Do you have a link to the conversation on the Facebook group? Earliest mention I could find is https://www.facebook.com/groups/CommanderX16/permalink/637566960327735 which came five months after the video.

(1) You wrote: "AFAIR, the PSG was part of the original design target of the Vera designer". That statement was being addressed by this point.

(2) It seems reasonable that this was David's understanding at that time because there had not been anything said to suggest otherwise. The timing of mentions I could find in the FB group are consistent with this. Again: do you have a link to something earlier that would square this?

(3) You wrote: "Given that the designer of Vera was including the PSG in any event". That statement was being addressed by this point. What do you think is being introduced that hasn't been said?

No, AFAIR, it wasn't in a post, it was in the discussion following a post, so no surprise if it didn't come up in a search ... searching Facebook comments is so hit or miss its often a waste of time.

The earliest reference I see in a topline item is Frank's October 16, 2019 edit of the CX16 Features and Specs document to include the Audio options still being determined, with 3 designs "being considered and tested at the moment including a Yamaha YM21512, a SAA1099 and a SID-like implementation in the video chip's FPGA", which is roughly a month after the mention by Dave that one of the three people doing the "heavy lifting" on the design "maybe" might put audio on the Vera. Given that sometime between the Pt. 2 video and a month later the PSG functions on the FPGA were being tested, the FB comment that Frank had originally wanted Vera to have the audio capabilities seems quite plausible.

 

 

Edited by BruceMcF

Share this post


Link to post
Share on other sites

I applaud you guys for debating/discussing this with restraint and trying to keep things cordial.  Maybe its the moderation policies keeping people in line, but I have learned a lot from your discussion and like to think the approach has been based on each person coming to the subject from a position of good faith. 

From the cheap seats (which is to say, from the perspective only of someone who signed up to this forum because I followed the project with an interest in seeing about buying an X16 eventually) I tend to think the need for an FPGA for video was obvious, but the question of sticking sound in the VERA, and then mass storage, etc., begins to treat that FPGA subsystem as a sort of cargo cult for further feature wish fulfilment.   Enthusiasts will each come to the purchase of getting an X16 from a perspective of balancing at least two considerations that will vary on a personal level:  (a) the generally amorphous but strongly impactful nostalgic purity instinct which, for example, causes a person to pick up a real C64 on eBay even at the risk of old hardware and a need for repairs, as opposed to grabbing a C64 MAXI from Amazon.  This retro "genuine cred" factor is something I tend to think of as close to a 'core principle' in 8BitGuy's videos on this project as one could ascertain, especially the "real CPU" and "off the shelf" stuff.   This first desire is balanced against (b) generally a much more generally "practical" set of considerations such as total cost, ease of programming, feature set, what the software base will look like and all that.

As someone who first followed the project thinking a purchase would be inevitable, I do feel my own balancing of these considerations impacted by how the project has evolved.   To me, it matters almost not at all 'when' the trajectory changed or who agreed, suggested, or pushed the change.   Handling sound by putting information into video device registers doesn't really scratch a retro itch, and makes me nervous because the VERA ports begin to feel like a more significant bottleneck the more resources have to share them.  And, I although I don't quite think I'm at this point, there will probably be people who throw up their hands and say "well, if I'm going to be programming for a virtual device on an FPGA, I might as well program a "virtual" VIC4 and quad SIDs on a Mega65 where I can use all my C64 experience" and we'll have to see if that camp might have a point.  For others, deletion of the YM2151 (which the tea leaves suggest to me is probably inevitable) will be the straw the breaks the camel's back, because at that point the assessment might be that the project would have become the "VERA computer."  At least one of my online acquaintances has expressed skepticism of a machine that presents a user experience of:  "use your cleverness to address 8 bit limitations merely as an interface to an arbitrary non-8-bit 'from scratch" design that actually does most of the work.   Having that real 8 bit CPU under the hood is awesome, but if all that CPU and logic does is provide a sort of (narrow)  onramp to all of the main "real" functionality on an FPGA, that might push people towards something more like a Color MAXIMITE or the like.    For yet others, more esoteric hardware considerations might be a problem.   Although I'm personally not fussed at all about the project enclosure selection leading to ATX power, recent addition of the AT-TINY, and other things leading to I2C and all that;  a few comments on TexElec's latest C15 video suggest there are people for whom this strongly alters the balance between nostalgic purity and practical considerations.   

I'll quit ruminating at this point, because truth to tell, my economics training (and the history of the computer industry in general) suggests that the the best price will have a strong bottom line advantage.   So for me its going to remain "wait and see" mode..     

Cheers guys, and again thanks for the informative and interesting discussion in this thread.  

  • Like 1

Share this post


Link to post
Share on other sites
16 minutes ago, Snickers11001001 said:

but the question of sticking sound in the VERA, and then mass storage, etc., begins to treat that FPGA subsystem as a sort of cargo cult for further feature wish fulfilment. 

 

16 minutes ago, Snickers11001001 said:

For others, deletion of the YM2151 (which the tea leaves suggest to me is probably inevitable) will be the straw the breaks the camel's back,

From what's been said repeatedly by the dev team, the hardware and design is pretty much set in stone at this point.  It shouldn't change anymore from where it is now, except to fix critical issues.  Mostly we'll just see software changes from here.

Share this post


Link to post
Share on other sites
4 hours ago, Ender said:

 

From what's been said repeatedly by the dev team, the hardware and design is pretty much set in stone at this point.  It shouldn't change anymore from where it is now, except to fix critical issues.  Mostly we'll just see software changes from here.

If that's the case, they should tweak the FAQ again.   The language in the sound section (changed just this year when they settled on deleting the SA1099) has a decidedly less than "set in stone" tone, referring to the VERA and YM2151 and saying that "one or both" will remain.   That, to me, ( especially as it was updated just last month) is what led to my speculation the YM2151 might be on the chopping block.   Personally, having once had a Shinobi arcade machine in my living room (ah the days of being a bachelor) I'm personally fond of the sound from that chip so I'd be pleased if it stayed in the design.   

Share this post


Link to post
Share on other sites
Posted (edited)
On 3/23/2021 at 5:57 PM, Snickers11001001 said:

If that's the case, they should tweak the FAQ again.   The language in the sound section (changed just this year when they settled on deleting the SA1099) has a decidedly less than "set in stone" tone, referring to the VERA and YM2151 and saying that "one or both" will remain.   That, to me, ( especially as it was updated just last month) is what led to my speculation the YM2151 might be on the chopping block.

It was mentioned in Kevin's YouTube video "Commander X16 Hardware Changes for Proto #2" - that was confirmed to be the official announcement that the banking control had moved.

(I don't have enough 6502 assembly experience to know if this is likely a problem in this context, but I know from decades of experience that the most likely address to be accidentally written to is address 0 - usually due to C code not checking if a pointer is null before using it. If that's a common problem in 6502 also, it's going to create nightmare debug scenarios.)

Edited by Wavicle

Share this post


Link to post
Share on other sites
29 minutes ago, Wavicle said:

(I don't have enough 6502 assembly experience to know if this is likely a problem in this context, but I know from decades of experience that the most likely address to be accidentally written to is address 0 - usually due to C code not checking if a pointer is null before using it. If that's a common problem in 6502 also, it's going to create nightmare debug scenarios.)

On the 6502, pointers are not used nearly as much as they are on modern systems. This is because most 6502 instructions can only indirect through the first 256 bytes of RAM, aka zero page. Any pointers must be copied into zero page before they can be used. This makes issues with null pointers far less likely. One of the reasons why banking control was moved to $00/$01 is because the C64 uses the same addresses for system control registers, including ROM banking.

  • Like 1
  • Thanks 1

Share this post


Link to post
Share on other sites
Posted (edited)
11 hours ago, Snickers11001001 said:

If that's the case, they should tweak the FAQ again.   The language in the sound section (changed just this year when they settled on deleting the SA1099) has a decidedly less than "set in stone" tone, referring to the VERA and YM2151 and saying that "one or both" will remain.   That, to me, ( especially as it was updated just last month) is what led to my speculation the YM2151 might be on the chopping block.   Personally, having once had a Shinobi arcade machine in my living room (ah the days of being a bachelor) I'm personally fond of the sound from that chip so I'd be pleased if it stayed in the design.   

Well, set in stone unless there is a show stopper problem. I would indeed expect a wave of FAQ updates after the Kernel gets updated to the "Rev kind of 3.0" board.

 

17 hours ago, Snickers11001001 said:

[1] I applaud you guys for debating/discussing this with restraint and trying to keep things cordial.

[2] From the cheap seats (which is to say, from the perspective only of someone who signed up to this forum because I followed the project with an interest in seeing about buying an X16 eventually) I tend to think the need for an FPGA for video was obvious, but the question of sticking sound in the VERA, and then mass storage, etc., begins to treat that FPGA subsystem as a sort of cargo cult for further feature wish fulfilment. 

[1] You get to the point where it is "arguing over taste". And if my recollection is accurate about what was said by one or another team member in Facebook discussion, it's not really possible to fault anybody for not seeing it, since searching Facebook comments is pretty useless ... and Facebook likes it that way, they don't want to be an archive of old conversations, they want an endless supply of new chatter.

[2] For me, the start of the snowball rolling on sound was when they dropped the AY3's. AFAIU, the AY3's are not new-old stock or pulls, they are clones (used in dirt cheap toys, etc., because at a certain volume using an existing design is cheaper than redesign). If 98%-99% of the pulls test good and there is good experience with the pulls that test out, but that applies at random to both the YM2151 and the watchamacallit SAA1099's, then that's 96%-98% of pairs of chips that test good. I reckon a combination of an AY3' and a YM2151's would have had a better shot at withstanding the siren call of the video chip contributor who wants it to be (AFAIR hearing recounted) a video & audio chip.

For the SD card, If Commodore 8bit era system designers were in some weird time machine scenario targeting SD cards, I reckon they'd do the same thing ... make a dedicated SD mode 0 SPI circuit, and put it in the chip with the fastest internal clock, which would have been the dot clock in the video chip. Building the correct 8bit single shot serial shift register with overflow to support the exact mode of SPI you need is just easier than a general purpose SPI master, and working off the dot clock beats working off Phi2 with a stick. I therefore have about as much trouble getting upset about accessing the SD card with an SPI circuit on Vera as I do about using an ATtiny84 in the power regulation / NMI front panel switch selection circuit.

 

Edited by BruceMcF
  • Like 2

Share this post


Link to post
Share on other sites
Unfortunately "official" info that is obsolete is something of a norm around here (at least for the last several months, hopefully this changes soon). In another thread discussing using the VIA's for banking control there was mention that "official announcements" had been made that banking control was now ZP $00/$01. The official announcement wasn't a topic thread in the official announcements forum, nor was it in the FAQ, the Wiki, the docs on GitHub, or supported by the emulator in the master branch. It was mentioned in Kevin's YouTube video "Commander X16 Hardware Changes for Proto #2" - that was confirmed to be the official announcement that the banking control had moved.

This is an unnecessarily critical and inaccurate comment, and isn’t the first time. It is not the tone we want for our forums. Please moderate your future comments before posting. I and others work extremely hard to keep the FAQ up to date and strongly dispute that “obsolete info is the norm around here”. In fact I do not believe there is one piece of obsolete info in the FAQ. And the FAQ is the single point that we send everyone to for the latest info. We are consistent about that.

We cannot control somebody outside the core team mentioning to you something that they saw in a video by Kevin, and that person you chatted to labelling it an official announcement. Criticising a team who are working for free for not copying every thing that is said in a video into the already extensive FAQ is unreasonable.

Michael is also not done with the new emulator version or the GitHub. You need to be more patient. The physical prototype will always be ahead of the GitHub.

You also cite a wiki but as I have mentioned before, and as is clearly stated in the wiki itself, it is not official and we do not run the wiki. Would you prefer we have the fans who do run it take it down permanently if it does not meet your requirements?

Finally please remember that this product has not even been released yet, nor have we taken a penny from anybody for it. We are offering unprecedented behind-the-scenes access to the development, which I don’t think has ever been done to this extent before even crowdfunding commences. Criticising us because we do not meet your high (and erroneous) standards will not be tolerated further.

This thread has also run its course, with some unfriendly moments before today, so I hope everybody can just take a breath and perhaps move onto a different topic.

Thank you for your understating.

  • Like 9

Share this post


Link to post
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.


×
×
  • Create New...

Important Information

Please review our Terms of Use