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Addressing logic


jbaum81
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The README on the master is to support the current emulator. If you use 0/1 it will fail in emulation. So, unless you have a physical board, this doesn't help you. Once the emulator is updated to reflect the latest hardware changes, then we can worry about what's "obsolete". 

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6 minutes ago, SlithyMatt said:

The README on the master is to support the current emulator. If you use 0/1 it will fail in emulation. So, unless you have a physical board, this doesn't help you. Once the emulator is updated to reflect the latest hardware changes, then we can worry about what's "obsolete". 

The Readme on the master branch supports the emulator on master branch. If you use 0/1 it should work just fine if you use the r2 board branch. (See this line which implements the zero page RAM bank select.)

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Well to clarify on that, the emulator hasn’t been updated because Micheal hasn’t received an updated board yet. However official announcements to the real hardware have been announced and that is the relevant and current data. Yes the emulator does need to be updated but it’s not getting updated till the person writing the emulator has the real hardware and can make sure that the emulator and real hardware behave the same. Much of this has very much been affected by the global circumstances. We would like to be moving much more quickly but sometimes we have to wait for updated components.

 

 

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55 minutes ago, Lorin Millsap said:

However official announcements to the real hardware have been announced and that is the relevant and current data.

Is that true? Flipping through the official announcements the closest I see is a short reply on the second page of discussion to the announcement that the second prototype boards have arrived. Isn't that obfuscated for an official announcement? I'm not trying to just kick dust here; it feels like even highly competent people are going to have difficulty finding non-obsolete information. I'm an engineer who has worked in, around, or close to VLSI and board design at Intel and Microsoft for nearly 20 years so I like to think I'm pretty competent at picking up on these things and I only knew about the change because Kevin mentioned it in the New Year's video.

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Is that true? Flipping through the official announcements the closest I see is a short reply on the second page of discussion to the announcement that the second prototype boards have arrived. Isn't that obfuscated for an official announcement? I'm not trying to just kick dust here; it feels like even highly competent people are going to have difficulty finding non-obsolete information. I'm an engineer who has worked in, around, or close to VLSI and board design at Intel and Microsoft for nearly 20 years so I like to think I'm pretty competent at picking up on these things and I only knew about the change because Kevin mentioned it in the New Year's video.

Kevin’s video is the one. There was no announce until the board with the changes was actually working.


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As far as I can tell jbaum81 is referring to this website ( http://wilsonminesco.com/6502primer/ )
It isn't exactly a wiki but it does contain a lot of reference material that I have come to expect out of a wikis.

Ah, okay that isn’t an official resource, just to be clear then.


Perifractic, X16 Visual Designer
http://youtube.com/perifractic
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14 hours ago, jbaum81 said:

I think I follow, but what have you gained by first splitting the upper 32k out? If we acknowledge that a1-14 still have to be evaluated? 

The latches I've chosen require OE to be off when latching, the logic I came up with there was AND the clock pulse with write and the logic that addresses the chip then invert OE as I bring the cp high. Not in that exact order of course, I do bring OE high well before CP going high. I attached my diagram above if your interested. 

With something like a 74xx373, you may be able to tie /OE to ground, because the latch outputs are tied to address lines on chips that won't be selected when LE is high on the bank register latches. That is, just because you have a tri-state latch doesn't mean tri-state is necessarily required in this case.

Evaluating A1-A15=0 can be done with two chips in one level logic ... two dual 4-input OR gates would be cleaner if they can be had ... though come to think of it, that should be A1-A15=R/W=0, which uses up all 16 inputs. If that is fast enough logic to be set up in one logic level before PHI2=1, then you can use PHI2 and A0 as the input into an active high 2x4 demux selected on A1-A15=R/W=0, with $0, $1 not connected and $2 and $3 as LE for the $0000 and $0001 latch, respectively.

It is entirely independent of the rest of the chip selects, so none of the other chip selects have to wait on the outcome of the latch logic.

 

Edited by BruceMcF
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19 hours ago, jbaum81 said:

I'd definitely prefer to just tie it to ground though if the output will literally just echo the state of the flipflops as they change. Here is the datasheet for the latch I chose. 

https://www.ti.com/lit/ds/symlink/sn74f574.pdf

Geez, where is my head?  Bank registers need to be initialized at power on.  That is easiest using a resettable flop, like the '273.

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I think I found my solution!!! 

Using some 8 bit comparators. All logic is >= 10ns at each phase. 

I think my only gap here is the flip-flop for the rom. I think I need to hold OE high with some pull down resistors on it's outputs to keep the rom on bank 0 for boot. Was thinking maybe a 555 timer tied to the yet to be created reset circuit.... The thought would be to hold RST low during power on with some additional logic to keep OE high long enough to execute an instruction to latch it at 00. Anyone have a better idea for boot?

 

jb6502 logic.PNG

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24 minutes ago, jbaum81 said:

Anyone have a better idea for boot?

Replace the '574 with '273, and use its built-in clear function.

Be careful mixing logic families.  'AC11032 VIH is not compatible with 'F521 VOH. 

You can replace all of the jelly bean logic used to generate both bank register clocks with a single '138, similar to BruceMcF's comment above.

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17 minutes ago, Lorin Millsap said:

So question. Not against people learning, but why are you attempting to clone a product we haven’t released yet?


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I started this adventure to build my own 6502 computer inspired by Ben Eater's video's. After I did that and wrote a little assembly I sort of decided that I didn't want to be on an island by myself and decided I'd maintain compatibility with the CX16. This way I get the experience of designing my own circuits (Note I have not asked for yours), and mine would be compatible with your software. To be clear I absolutely 1000000000% plan on supporting this project and will purchase a CX16 once released, but ultimately would like to run my own board that way I'm familiar with the hardware and able to support it myself. Soldering chips to someone else's design doesn't quite tickle my fancy lol. Also I did email David about this, not necessarily to ask permission, but he is aware of what I'm up to and didn't take any issue with it. If I'm oversharing or offending anyone on the project please let me know, obviously my interest isn't to 'clone' it in any way to undermine or hurt the project. 

 

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14 hours ago, Perifractic said:

 


What Wiki is that?


Perifractic, X16 Visual Designer
http://youtube.com/perifractic

 

Apologies, I was actually referencing the programming guide on GitHub, sorry for the confusion. 

 

19 minutes ago, picosecond said:

Replace the '574 with '273, and use its built-in clear function.

Be careful mixing logic families.  'AC11032 VIH is not compatible with 'F521 VOH. 

You can replace all of the jelly bean logic used to generate both bank register clocks with a single '138, similar to BruceMcF's comment above.

As for mixing logic, are you referencing the differences between TTL and CMOS? Most I could find on those is the voltages considered high/low, which, as far as I understand, shouldn't really make any difference in my logic? Can you clarify or point me in the right direction as to what makes them incompatible? 

Thanks for the pointers, I'll check into that. 

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35 minutes ago, jbaum81 said:

are you referencing the differences between TTL and CMOS? Can you clarify or point me in the right direction as to what makes them incompatible? 

Yes, TTL and CMOS have different specifications for low and high voltage levels.  Let's assume a minimum VCC of 4.5V for this example.

For the F521, a "1" at the output means a voltage greater than 2.5V.  This is the VOH(min) parameter in the datasheet.

For the AC11032, a "1" at the input is guaranteed to be recognized only if the voltage is 3.15V or greater.  This is the VIH(min) parameter in the datasheet.

So a perfectly valid "1" for the F521 could be wrongly interpreted as a "0" by the AC11032.  Obviously that would be bad.  If you ever wondered why there are both AC and ACT logic families this is the reason.  ACT input voltage thresholds are shifted downwards to be compatible with TTL output voltages.

This article has a more complete explanation:  https://www.allaboutcircuits.com/textbook/digital/chpt-3/logic-signal-voltage-levels/

As an aside, in your last schematic you could connect RW to that unused 'F521 input and save some glue logic.

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48 minutes ago, picosecond said:

Yes, TTL and CMOS have different specifications for low and high voltage levels.  Let's assume a minimum VCC of 4.5V for this example.

For the F521, a "1" at the output means a voltage greater than 2.5V.  This is the VOH(min) parameter in the datasheet.

For the AC11032, a "1" at the input is guaranteed to be recognized only if the voltage is 3.15V or greater.  This is the VIH(min) parameter in the datasheet.

So a perfectly valid "1" for the F521 could be wrongly interpreted as a "0" by the AC11032.  Obviously that would be bad.  If you ever wondered why there are both AC and ACT logic families this is the reason.  ACT input voltage thresholds are shifted downwards to be compatible with TTL output voltages.

This article has a more complete explanation:  https://www.allaboutcircuits.com/textbook/digital/chpt-3/logic-signal-voltage-levels/

As an aside, in your last schematic you could connect RW to that unused 'F521 input and save some glue logic.

 

I think I was under the assumption that eventually the signal levels would reach 0 or 5v and that'd be totally okay given the amount of time, of course this would be predicated on stable power, right? I'll definitely look into alternatives, but finding low propagation delay logic gates has been somewhat challenging. 

As for running RW through the grounded input on the low address range F521, it's definitely a good idea, and would work, but I'm using the CLKWR signal out of that AND gate for write enable on the ram chips anyways. I don't think it's required, but I do have the time and wanted to try to make sure all address and select logic is taking place on low clock, with writes only occurring during high clock. I got lazy and didn't give the same consideration for reads, but meh, not really necessary, at least as far as I can tell. Trying to learn, the best I can, from my understanding of the mistakes Adrian pointed out on the 2nd proto board with timing. 

As an aside, I just updated my PCB layout and seen all the logic IC's and their associated rats nests drop into my, so far, beautifully laid out board and traces. I admit, I leaned back in my chair and started wondering why in the hell I'm trying to do this all through hole lol. I may just scrap my progress and switch to SMD. If I can figure out how to program the ROM while it's soldered onto the board I may switch to SMD and try to shoot for some faster RAM/ROM chips and maybe shoot for 12mhz.... Oh I think I could use a clock divider and leverage another flipflop in the IO area to change the speed on the fly. I think that'd be kind of fun.

 

 

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36 minutes ago, jbaum81 said:

I was under the assumption that eventually the signal levels would reach 0 or 5v

That's not an unreasonable intuition but TTL doesn't work that way.

41 minutes ago, jbaum81 said:

Trying to learn, the best I can, from my understanding of the mistakes Adrian pointed out on the 2nd proto board with timing.

Timing is an interesting subject.  If you are interested in testing your understanding, can you explain which violated timing parameter Adrian fixed on proto #2?

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5 hours ago, jbaum81 said:

I think I found my solution!!! 

Using some 8 bit comparators. All logic is >= 10ns at each phase. 

I think my only gap here is the flip-flop for the rom. I think I need to hold OE high with some pull down resistors on it's outputs to keep the rom on bank 0 for boot. Was thinking maybe a 555 timer tied to the yet to be created reset circuit.... The thought would be to hold RST low during power on with some additional logic to keep OE high long enough to execute an instruction to latch it at 00. Anyone have a better idea for boot?

 

jb6502 logic.PNG

Depending on what you're trying to achieve, you might consider replacing most of those components with the Atmel ATF16V8C. SPLDs are the evolutionary descendants of the PAL chips used by early computers like the C64. Two of these cascaded should give you the ability to do address decoding of 16 address lines + R/W in 15ns (maybe 15 address lines + R/W, I'm a little uncertain what the deal with I9/OE is). Less than $2 each and they're reprogrammable.

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On 3/6/2021 at 10:59 AM, jbaum81 said:

 

I think I was under the assumption that eventually the signal levels would reach 0 or 5v and that'd be totally okay given the amount of time, of course this would be predicated on stable power, right? I'll definitely look into alternatives, but finding low propagation delay logic gates has been somewhat challenging. 

As for running RW through the grounded input on the low address range F521, it's definitely a good idea, and would work, but I'm using the CLKWR signal out of that AND gate for write enable on the ram chips anyways. I don't think it's required, but I do have the time and wanted to try to make sure all address and select logic is taking place on low clock, with writes only occurring during high clock. I got lazy and didn't give the same consideration for reads, but meh, not really necessary, at least as far as I can tell. Trying to learn, the best I can, from my understanding of the mistakes Adrian pointed out on the 2nd proto board with timing. 

As an aside, I just updated my PCB layout and seen all the logic IC's and their associated rats nests drop into my, so far, beautifully laid out board and traces. I admit, I leaned back in my chair and started wondering why in the hell I'm trying to do this all through hole lol. I may just scrap my progress and switch to SMD. If I can figure out how to program the ROM while it's soldered onto the board I may switch to SMD and try to shoot for some faster RAM/ROM chips and maybe shoot for 12mhz.... Oh I think I could use a clock divider and leverage another flipflop in the IO area to change the speed on the fly. I think that'd be kind of fun.

 

 

Almost positive he mentioned the vera needing writes on high clock, and im thinking the audio chip, but simce none of the tests were working im thinking there might have been a yiming issue woth the rom. I dont remeber the specifics as it relates to the cx16, but it motivated me to try to read and understand the data sheets. Ben Eater also has some pretty good material on understanding it. My main take away was to attempt to have address and and data stable prior to writes, the 6502 doesnt seem as sensetive on reads as long as its stable by, iirc, something like 30ns from the falling edge. 

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2 hours ago, jbaum81 said:

Almost positive he mentioned the vera needing writes on high clock, and im thinking the audio chip, but simce none of the tests were working im thinking there might have been a yiming issue woth the rom. I dont remeber the specifics as it relates to the cx16, but it motivated me to try to read and understand the data sheets. Ben Eater also has some pretty good material on understanding it. My main take away was to attempt to have address and and data stable prior to writes, the 6502 doesnt seem as sensetive on reads as long as its stable by, iirc, something like 30ns from the falling edge. 

The YM sound chip needs A0 to be set up minimum T_AS or more before /CS and/or /WR and/or /RD, and remain set up until after they are released, because A0 decides whether the register address latch or the register with the currently latched address is being selected, so the timing is not that different from a PIC style bus. If A0 can be asserted early enough before PHI2 rises, having /WR /RD and /CS synchronous with PHI2=1 would ensure that. The Address/Data port is not strictly clocked ... the clock input is for operation of the FM synthesis ... the cycles are from the later of /CS and either /WR or /RD, respectively, through to the earlier of CS and either WR or RD, respectively.

(I would not be surprised if the OPM chips they are using are the CMOS versions, and since the datasheet I have is the original OPM, the minimum set-ups, holds and releases may be shorter than the timing I am looking at.)

By contrast, the VIA's need address, /CS and R/W to be setup tACR/tACW before PHI2=1, which at +5VCC is given as a minimum of 10ns, so R/W and /CS synchronous with the clock would violate that.

And Vera, the SRAM and the FlashROM, I wouldn't have any idea, all of that is well after my time.

Edited by BruceMcF
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So much to learn and so little time haha. At least I can say it's a hell of a lot cheaper of a hobby than my previous reef keeping or RC Helicopter hobbies. I'm thinking it might be time to retire the old DSO nano scope and move into a benchtop 2 channel scope. 

I can't believe how cheap it is to have boards printed now. Last time I had a board done was about 10 years ago and you had to join in on a group buy type thing and wait till the board was filled and printed in china. Took like 6 weeks. 

 

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1 hour ago, jbaum81 said:

I can't believe how cheap it is to have boards printed now. Last time I had a board done was about 10 years ago and you had to join in on a group buy type thing and wait till the board was filled and printed in china. Took like 6 weeks. 

Interestingly, you are still effectively waiting for the board to get filled and printed, but the manufacturer has streamlined the process to the point that the wait queue is on the order of a few hours. E.g. the thumb nail of this video which shows at least two different PCBs or around 16:09 there is a shot of a board that looks like it has 7 or 8 different designs on it. The last time I checked on having a board made locally, it was 20x more expensive and would take twice as long to get it. I'm pretty sure they catered to companies that could not offshore PCB production for secrecy reasons.

 

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On 3/11/2021 at 2:36 AM, BruceMcF said:

VIA's need address, /CS and R/W to be setup tACR/tACW before PHI2=1

Exactly.  Gating the raw decoded chip select with PHI2 obviously puts /CS well after PHI2 rise.  They missed the setup window.

On 3/11/2021 at 2:36 AM, BruceMcF said:

having /WR /RD and /CS synchronous with PHI2=1 would ensure that

Controlling only the YM2151 /CS is sufficient.  All of the data timing parameters reference the last control signal change.

Zero wait state operation isn't so easy at 8MHz.  Access time is 180ns so reads are totally broken.  But those are used only to check interrupt status.  Interrupts might not even be connected.  The easy fix is to simply disallow reads.

Zero wait state writes cannot meet the timing requirements by using PHI2 edges for pulse forming.  Using the typical design pattern will violate Tcw(100ns) and Tds(50ns).  That probably works fine on the bench at room temp but may not be reliable across a production run.  Some kind of /CS pulse stretching is needed to satisfy the datasheet requirements.

After the VIA timing problems I imagine the team reviewed every chip's timing requirements, and have a plan to address this in proto#3.  Or maybe they just plan to screen YM2151s before using them.

On 3/11/2021 at 2:36 AM, BruceMcF said:

(I would not be surprised if the OPM chips they are using are the CMOS versions, and since the datasheet I have is the original OPM, the minimum set-ups, holds and releases may be shorter than the timing I am looking at.)

Do such versions exist?  I have never encountered a reference that suggests this, let alone a datasheet that quantifies the timing differences.

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2 hours ago, picosecond said:

Zero wait state operation isn't so easy at 8MHz.  Access time is 180ns so reads are totally broken.  But those are used only to check interrupt status.  Interrupts might not even be connected.  The easy fix is to simply disallow reads.

Hmm - I've been wondering whether the real YMs could support reads @8MHz or not. The YM read also has one more important functionality than IRQ checking - the busy flag.

This isn't an issue in the emulator because the YM2151 library being used doesn't emulate the chip's busy state anyway. The real chip requires 64 YM clock cycles after writing data before you can write to it again. The real HW will obviously have this issue, and the fastest way to write data to it reliably is to read the busy flag until it's zero, then do your write. (That's how the sound CPU does it in Street Fighter II, for instance). Otherwise, you have to just do some busy loops which probably take an average of n/2 clock cycles longer than necessary away from your program if you just busy loop yourself.

Then again, that would just become one of the challenges of coding on the platform, eh?

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