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On 5/3/2021 at 11:51 PM, Roman K said:

@ZeroByte I mean overriding the memory, not another device. Like my device with RAM on it listens to the address bus and responds to the CPU if some memory address is requested. If there is memory chip already responsible for that address, how is that conflict resolved? That should happen on real devices. Or there is a dedicated IO range that is not handled by RAM and can be used by devices?

There is a dedicated IO range that can be used by devices ... that is the sets of 32byte control register addresses for I/O in $9FFF, which three sets used by the system and five available on the expansion slots. Beyond that, DMA, "Direct Memory Access" would be the way to go, just take over the bus and write the data directly to the desired RAM location. At the upper limit, where only one side of the transfer is on the CX16 bus, that can proceed at one byte per cycle, so a "binary page" of 256 bytes can be moves in 256 cycles, whereas a general purpose (zp),Y copy is:

COPY: LDY #0
COPY1: LDA (SRC),Y : STA (DEST),Y : INY : BNE COPY1
COPY2: RTS

Where if that is page-aligned, that is 15 cycles per byte moved plus overhead.

Now, a page at a time is a lot of time for interrupts to be suspended, so a more general purpose DMA board might be oriented around 16byte, 32byte or 64byte chunks, depending on how long you figure you can leave interrupts suspended without messing with performance. If the DMA chunk reference autoincrements and the setting of the lower byte of the main bus target or destination chunk register triggers the DMA, you might have a loop of:

PASTE: ; A=chunk lo, Y=target-hi, as chunk reference, X = #chunks, 0-base, DMA source address is already set-up
PASTE1: STY dmatrg+1 : STA dmatrg : DEX : BEQ PASTE3
PASTE2: INC dmatrg : DEX : BNE PASTE2
PASTE3: RTS

That's an inner loop of 1.2-1.7 clocks per byte moved, plus overhead, for chunks of 16-64 bytes. Ideally the auto-increment system for the DMA RAM would be the same auto-increment system as for Vera, both to reduce the amount of new things that need to be learned, and also to integrate with Vera.

For Vera, and conceivably also for other I/O, you'd also have a fixed IO page target address function:

VPASTE: ; A=IOaddr, X = #chunks, 0-base, I/O target settings, DMA source address is already set-up
VPASTE1: STA dmaiotrg : DEX : BNE PASTE1
VPASTE2: RTS

 

Edited by BruceMcF
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