Jump to content

Two 6502 System


rje
 Share

Recommended Posts

3 minutes ago, Kalvan said:

Why store each entire page web-cache style?  I''m pretty sure only storing the file location and/or previous answers to questions would have been sufficient.  Did the kiosk also feature artificial intelligence routines that required the user to input entire answers to essay questions?

As I wrote in another reply that you might not have seen yet, it was just not having enough time to do the design and think through the issues. This was a simple implementation and not a problem if you only had a few pages, and the back button worked instantly. But the kiosk did have some screens with potentially long input fields (not quite essay questions) that a user would use a touch screen keyboard to enter search criteria to wade through multiple terabytes of content trying to find what they wanted.

Also learned at that job (and it would have been obvious if social media had been a big thing yet, but it was really just getting started): there are lots of bad spellers out there, so many times people would type in some search criteria and misspell names and not find what they wanted, even though we had it. It is complicated by the fact that many artists use creative or leet spelling (P!nk for example) which just doesn't match pink. So I wound up implementing a fuzzy search module that would take the words typed and match them to all the words in our dictionary. It meant more time at kiosk start to build tables that could be reused through the run of the application, but people actually started finding what they wanted because matches were sorted by edit distance. There might be a few exact matches at the top (legitimate matches for pink that are not p!nk) but then just below that would be p!nk since it had an edit distance of one and thus was a better match than say "sinatra".

  • Like 3
Link to comment
Share on other sites

On 7/26/2021 at 5:25 AM, Guybrush said:

Two 6502's could also run on opposite phases of the clock, like 6510 and VIC-II run in the C64 and access memory without DMA or dual-port RAM. If they need to signal each other, they could use a VIA to signal interrupts. I'm not sure if both could access the same hardware (except memory, of course) because the timings might be a problem, but if you dedicate one of them to handle I/O, sound or video, then they don't have to both access all of the hardware.

They should still have their own RAM in part of their address space ... but this could definitely be used for communication between the CPU's. If one are of the common RAM space is allocated to W#1 and R#2 and another is allocated to W#2 and R#1, you get the effect of using dual port RAM for channels without the expense of dual port RAM.

Link to comment
Share on other sites

But there is no need for dual-port RAM if the processors run on opposite phases of the system clock since memory accesses never occur at the same time, they are interleaved. There's also no need for dedicated RAM (apart from zero and stack pages), it would only complicate loading the data and code for the second processor. Let the programmers use RAM as they please.

Link to comment
Share on other sites

3 hours ago, Guybrush said:

But there is no need for dual-port RAM if the processors run on opposite phases of the system clock since memory accesses never occur at the same time, they are interleaved. There's also no need for dedicated RAM (apart from zero and stack pages), it would only complicate loading the data and code for the second processor. Let the programmers use RAM as they please.

I think the only point is that some tasks will work better if the individual CPUs have access to private RAM that cannot be overwritten (deliberately or otherwise) by the other CPU. One memory map that comes to mind would divide the address space into two 32K chunks. The first half is private to a CPU (so each CPU gets its own zero page and stack; the stack in particular you do not want to share directly between these CPUs!). The second half is shared address space. Each bank can contain any combination of RAM / IO / ROM desired, including an ability to do bank switching to give access to even more public or private RAM / ROM.

Ultimately it doesn't have to be an even 32K split, but I think at minimum you'd want the private stacks, and probably private ZP, and perhaps even another page or two of private non-shared space.

Link to comment
Share on other sites

Idea for this hypothetical dual 6502 machine.

64K of private RAM for CPU 0
64K of private RAM for CPU 1
16M of shared RAM (256 64K banks)
16M of shared ROM (256 64K banks)

ZP register to control which page of shared RAM is seen per CPU
ZP register to control which page of shared ROM is seen per CPU
ZP register to control the size of private RAM / shared ROM windows

8 values of private RAM window would allow sizes (starting low) of 512B, 1K, 2K, 4K, 8K, 16K, 32K, 63.5K (so the top 512B of address space is always "ROM")
8 values of shared ROM window would allow sizes (starting high) of 512B, 1K, 2K, 4K, 8K, 16K, 32K, 63.5K (so the bottom 512B of address space is always private RAM)
The two remaining bits could be used to enable / disable each of the windows if one really wanted to be extra cute, but more than likely you just leave them reserved or unused.

Some rule would be defined to control which of private RAM / ROM takes precedence if incompatible windows were chosen.

So each CPU can control how much address space is used for each purpose in a relatively straightforward way.

There is no IO in that map. Borrowing a page from X16, I would reserve a single page of address space for IO. In my model, page FF is always ROM bank 0 (effectively; could just copy the same page to all ROM banks so that it never matters what ROM bank is active) and would include the ROM vectors and support code to handle RESET/IRQ/NMI vectors. page FE would always be IO space.

So the minimum private RAM size of 512 covers ZP and stack. The minimum shared ROM space covers IO and vectors.

Okay, someone go build it! 🙂

Note / disclaimer: This is just a thought exercise, not a serious suggestion of how to design such a machine. Just riffing on the "let each CPU do what it wants" idea and dialing the amount of RAM and ROM up to 11 (at least 11 relative to the 6502 architecture).

Edited by Scott Robison
Link to comment
Share on other sites

1 hour ago, Scott Robison said:

...

Some rule would be defined to control which of private RAM / ROM takes precedence if incompatible windows were chosen.

So each CPU can control how much address space is used for each purpose in a relatively straightforward way.

There is no IO in that map. Borrowing a page from X16, I would reserve a single page of address space for IO. In my model, page FF is always ROM bank 0 (effectively; could just copy the same page to all ROM banks so that it never matters what ROM bank is active) and would include the ROM vectors and support code to handle RESET/IRQ/NMI vectors. page FE would always be IO space.

So the minimum private RAM size of 512 covers ZP and stack. The minimum shared ROM space covers IO and vectors.

Okay, someone go build it! 🙂

Note / disclaimer: This is just a thought exercise, not a serious suggestion of how to design such a machine. Just riffing on the "let each CPU do what it wants" idea and dialing the amount of RAM and ROM up to 11 (at least 11 relative to the 6502 architecture).

In the asymmetric version, I'm going to be more parsimonious with memory: 1 32K RAM and 4 512K RAM chips, and a 512K FlashROM.

CPU#1 / CPU#2 divided into 16K slots:
$0000-$3FFF Local RAM. ZP at $00xx, Stack at $01xx, Device page at $03xx
$4000-$7FFF Local RAM / Common RAM1
$8000-$BFFF Common RAM2
$C000-$FFFF ROM

3bits in one memory byte controls the base within 128K of ROM
5bits in the same memory byte controls the RAM1 base within 512K of RAM
1bits in the second memory byte controls whether Local or Common RAM1 are selected.
5bits in a second memory byte controls the RAM2 base within the 512K of RAM

Also CPU#1:
One memory control byte provides the high two bits of the external RAM for CPU#1 and CPU#2 and ROM for CPU#1. One bit controls ROM for CPU#2, which has the high bit tied high from ROM segment select.

When accessing ROM, or when accessing RAM when the RAM segments are the same, inverted clocks allow the use of "first come, first served" ... if selecting a chip the other CPU has selected in the previous half cycle, that CPU is suspended with RDY until the deselect and that CPU's rising clock, so for that CPU, the first clock phase will have just been stretched one clock cycle.

 

Edited by BruceMcF
Link to comment
Share on other sites

1 hour ago, Starsickle said:

This would be better off like a Dual Core computer but with entire chips. XD Two 6502s, a ROM controller acting as the thread/task manager (HAAAHAHAHAHA) and for the awesome power of...6MHz.

In what way?

Link to comment
Share on other sites

On 8/2/2021 at 5:27 PM, BruceMcF said:

In what way?

Well, It kinda fits the way we have our computers right now, doesn't it? There's an Arithmetic CPU and a whole other computer inside our computer doing more specific sorts of computations. I'm not sure how good the 6502 would be at that, but I don't see why you could have it designed as OP. In my Morning-no-coffee head, I'd say the bottleneck would still be the rate of synchronization between the two for tasks. I'm not sure what it'd be really good for in the world of 8 bits...

The previous discussion really centered around arranging the electrics of the memory spaces, but my gut tells me that anything that creates more complexity invites errors.

Don't want to be negative about the discussion though - the other posters have brought up some challenges in design, and I'm trying to look at it from other angles.

Edited by Starsickle
Link to comment
Share on other sites

4 hours ago, Starsickle said:

Well, It kinda fits the way we have our computers right now, doesn't it? There's an Arithmetic CPU and a whole other computer inside our computer doing more specific sorts of computations. I'm not sure how good the 6502 would be at that, but I don't see why you could have it designed as OP. In my Morning-no-coffee head, I'd say the bottleneck would still be the rate of synchronization between the two for tasks. I'm not sure what it'd be really good for in the world of 8 bits...

It seems like one of the things we know secondary general purpose CPUs were good for in the world of 8bit, playing audio, gives some idea about how to avoiding creating a bottleneck in whatever synchronization is necessary between the tasks. The point there was freeing up the main CPU from the necessity of constantly interrupting it's program execution to do another step in playing an audio sequence, having the secondary CPU keep the audio playing while the main CPU only has to make sure to keep it fed with the data as to what to play next.

  • Thanks 1
Link to comment
Share on other sites

This thread should be in the non-cx16 retro channel, but:
I've been thinking of tinkering with two 65c02s to build a breadboard machine. The first would be the main system, the secondary would handle screen and keyboard (ala terminal). They'd communicate through 6522's. The secondary would just take VT52 or VT100 style codes for video as input and send keyboard / escape code response codes back as output. That would free up the main CPU to run full bore, while the terminal CPU could buffer and state-machine the ANSI codes and handle keyboard voodoo while in vblank/hblank when driving video.

  • Like 1
Link to comment
Share on other sites

28 minutes ago, codewar65 said:

This thread should be in the non-cx16 retro channel, but:
I've been thinking of tinkering with two 65c02s to build a breadboard machine. The first would be the main system, the secondary would handle screen and keyboard (ala terminal). They'd communicate through 6522's. The secondary would just take VT52 or VT100 style codes for video as input and send keyboard / escape code response codes back as output. That would free up the main CPU to run full bore, while the terminal CPU could buffer and state-machine the ANSI codes and handle keyboard voodoo while in vblank/hblank when driving video.

I was thinking of something similar a couple days ago. Except I'm not a hardware guy typically. So I bought the Ben Eater kits and just starting putting them together tonight to try to get a handle on some of this kind of stuff. Not the exact split, but the separate CPUs with their own RAM and communicating through VIAs.

Good luck!

Edited by Scott Robison
  • Like 1
Link to comment
Share on other sites

14 minutes ago, Scott Robison said:

I was thinking of something similar a couple days ago. Except I'm not a hardware guy typically. So I bought the Ben Eater kits and just starting putting them together tonight to try to get a handle on some of this kind of stuff. Not the exact split, but the separate CPUs with their own RAM and communicating through VIAs.

Good luck!

I'm old school and love old dumb terminals! I was thinking of building a 6502 based VT100 terminal VERA. haha
I was actually thinking of grabbing Ben's kit as well, but want to get a better breadboard setup.
And writing my own terminal, I could 'add' my own special codes to redefine the character glyphs, play sound, sprites, etc. Even upload 65c02 code via ANSI to run as a background process and report back on a separate VIA port with results.
 

  • Like 1
Link to comment
Share on other sites

40 minutes ago, codewar65 said:

I'm old school and love old dumb terminals! I was thinking of building a 6502 based VT100 terminal VERA. haha
I was actually thinking of grabbing Ben's kit as well, but want to get a better breadboard setup.
And writing my own terminal, I could 'add' my own special codes to redefine the character glyphs, play sound, sprites, etc. Even upload 65c02 code via ANSI to run as a background process and report back on a separate VIA port with results.

It's good that you have an actual use for it, and nothing wrong with dumb terminals. In my case it was just a solution in search of a problem. 🙂

Link to comment
Share on other sites

47 minutes ago, Scott Robison said:

It's good that you have an actual use for it, and nothing wrong with dumb terminals. In my case it was just a solution in search of a problem. 🙂

'Dumb' terminal is a term, for a terminal. Some weren't so dumb. 😉 I am just looking to offload cycles onto another processor with dedicated capabilities, like how C64's 'talked' to disc drives with their own 6502s.

 

  • Like 2
Link to comment
Share on other sites

Right, I remember dumb terminals. My first programming class in college was FORTRAN 77 which was hosted on one campus mainframe and we accessed it via 3270-style terminals. Later I worked for a company that put terminal emulation software in first responder vehicles so they could access the same systems they'd access from the office. I'm sure by now it's been replaced with web based terminal emulation, though given how slow government can be at times to change, who knows. It has been probably 18 years since I last had a clue about what that company was doing.

Link to comment
Share on other sites

3 hours ago, Scott Robison said:

Right, I remember dumb terminals. My first programming class in college was FORTRAN 77 which was hosted on one campus mainframe and we accessed it via 3270-style terminals. Later I worked for a company that put terminal emulation software in first responder vehicles so they could access the same systems they'd access from the office. I'm sure by now it's been replaced with web based terminal emulation, though given how slow government can be at times to change, who knows. It has been probably 18 years since I last had a clue about what that company was doing.

Yes, when I was a Junior, the Freshmen got to use terminals for Fortran 77 class instead of having to use punch cards. I was so jealous.

Link to comment
Share on other sites

7 hours ago, BruceMcF said:

Yes, when I was a Junior, the Freshmen got to use terminals for Fortran 77 class instead of having to use punch cards. I was so jealous.

I missed the punched card era by just a few years. I never had to use them (or paper tape). However, I saw plenty of them. The professor of that FORTRAN class had a ton of punch cards, some unused, some punched. He would have several on him at all times and would use them for note cards.

One reason why I got the TA job a couple years later: I found a bug in the mainframe compiler. Of course, it seems every student says that at some point in time, but I really did. He would not believe it until I was able to demonstrate that my program worked on the PC version of the compiler from the same vendor (WATFOR77) and only had problems on the mainframe. 🙂 

Edited by Scott Robison
  • Like 1
Link to comment
Share on other sites

  • 2 weeks later...
5 hours ago, Scott Robison said:

You need available IO lines in order for the two to communicate. I don't know exactly what hardware the X8 will be based on, but I doubt it will have sufficient IO lines to accomplish this task.

Well, we don't have many details of the X8, but if it allows an RTC, then it may have an I2C channel for communication. If that is brought out on the board to a pin header, then a two wire ribbon cable could connect it to the CX16 I2C.

But part of the cost savings compared to the CX16e is that with the 128K SPRAM all of the RAM it uses, it doesn't have to bring data and address buses out.

And we know that when the Vera FPGA moved from 8 registers addressed on the system bus to 32, which is two more pins, they also pulled out the serial port, for lack of pins, So if the LX8 is allocating pins to the USB, and to things like supporting an I2C bus for a RTC, then they wouldn't have the pins to plug it into a CX16p slot.

Edited by BruceMcF
  • Like 1
Link to comment
Share on other sites

6 hours ago, Fenner Machine said:

What if you could connect an X8 to an expansion slot on the X16?

What if pigs could fly? Would we need to invest in stronger umbrellas?

"An X8 that could be tweaked to add an expansion slot" is the CX16e, it's not the X8. It's always easy to come up with a "better" design that doesn't "suffer from the limits" of a particular design ... if you free yourself from having to live within the real world constraints that led to those limits.

Edited by BruceMcF
  • Like 1
Link to comment
Share on other sites

39 minutes ago, BruceMcF said:

What if pigs could fly? Would we need to invest in stronger umbrellas?

"An X8 that could be tweaked to add an expansion slot" is the CX16e, it's not the X8. It's always easy to come up with a "better" design that doesn't "suffer from the limits" of a particular design ... if you free yourself from having to live within the real world constraints that led to those limits.

I don't even care about an expansion slot. I just want a enough of GPIO that we can have a serial port. Give me a UART and I can talk to the world. 

 

Link to comment
Share on other sites

2 minutes ago, TomXP411 said:

I don't even care about an expansion slot. I just want a enough of GPIO that we can have a serial port. Give me a UART and I can talk to the world. 

Wouldn't you need a WART to talk to the world? I guess the world is part of the "universal" charter of the UART. #insertdadjokegroanhere

Link to comment
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

 Share

×
×
  • Create New...

Important Information

Please review our Terms of Use