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Two 6502 System


rje
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4 hours ago, TomXP411 said:

I don't even care about an expansion slot. I just want a enough of GPIO that we can have a serial port. Give me a UART and I can talk to the world.

The lack of the expansion slot is the big downside to me for the CX16e ... for instance, no expansion slot, no bus mastering 65816 card.

If both the LX8 and CX16 were on offer, but neither of the real CX16 boards, I would likely getting the cheaper LX8 and hold out hoping the CX16c crowdfunding gets launched.

And as far as tweaks, tweaking the LX8 USB so it supports a hub and serial seems like a lot less of an ask than actually totally ditching Frank's board design and doing a new one and calling it the X8.

Edit: Never mind, it uses a WiFi modem to emulate a serial port connection, so that last tweak is not as high priority after all. For me, the "tweaks", any of which might required a larger resource FPGA, are, in order of my own personal priority:

(1) Access Vera RAM using the CX16 I/O page approach in addition to the native "roving page" approach.
(2) Include a soft YM2151 core
(3) A VIA core supporting a 3.3v version User Port via block pin header
(4) An FPGA with enough RAM resources to have 7 or more High RAM Banks (eg, if Block RAM that can be accessed as 32K RAM, implement $0000-$7FFF in Block RAM to free up more High RAM banks in SPRAM).

Edited by BruceMcF
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On 7/25/2021 at 11:25 PM, Guybrush said:

Two 6502's could also run on opposite phases of the clock ...

Did anyone on this thread already mention that this is exactly what the big CBM disk drives did? The 4040, 8050, 8250, etc...?

One 6502 was doing the IEC bus and file stuff and the other did block level disk access. They would communicate through memory locations.

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11 minutes ago, pzembrod said:

Did anyone on this thread already mention that this is exactly what the big CBM disk drives did? The 4040, 8050, 8250, etc...?

One 6502 was doing the IEC bus and file stuff and the other did block level disk access. They would communicate through memory locations.

I knew the drives had their own CPU but I did not realize (or my old brain forgot) that they had multiple CPUs working collaboratively. Thanks for the lesson / reminder!

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12 hours ago, Scott Robison said:

I knew the drives had their own CPU but I did not realize (or my old brain forgot) that they had multiple CPUs working collaboratively. Thanks for the lesson / reminder!

It's quite fascinating, really, and also provides a nice study in software architecture heritage. The 1541's DOS still shows this structure, only it simulates the second CPU with an interrupt driven disk controller routine. The job codes in the zero page that the file system and the disk controller communicate through - that was the shared memory in the 2-CPU drives.

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