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Change of product direction, good and bad news!


What should we do?  

341 members have voted

  1. 1. Should we release the Commander X8?

    • Yes, it should replace Phase-3. It's good enough.
    • Yes, but you should still offer a Phase-3 Commander X16 eventually too.
    • No, don't release the X8, stick with the original plan.
  2. 2. Should we still make a Phase-2 product?

    • Yes, Phase-2 is what I want
    • No, skip and go straight to Phase-3
  3. 3. For the X16 Phase-1, do you prefer a kit or a somewhat more expensive pre-assembled board?



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2 minutes ago, TomXP411 said:

What’s interesting is there does appear to be some sort of serial interface on the CX8. Apparently, the ESP32 is connected to the FPGA and allows code to be loaded through WiFi.

The ice40up5k has hardware SPI and I2C units, two of each.  I imagine CX8 is using one of these.  These units do not have dedicated IO, so using them isn't free.

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23 minutes ago, TomXP411 said:

What’s interesting is there does appear to be some sort of serial interface on the CX8. Apparently, the ESP32 is connected to the FPGA and allows code to be loaded through WiFi.

Although with a bit more known than two days ago, still, without a specification list, its not clear if that would be in the actual X8 ... it might be a development board feature not included in the finished product. If not, I would hope at least there is serial device support over the USB.

There is not yet code to run the big-banged serial port, and obviously the UART was left out, so there will be a speed limit on the serial port.

I figure the odds of the bit banged serial port being left out is a lot lower than the odds of Basic being left in roughly its current state, with a O^2 garbage collector and far from running like a champ.

Edited by BruceMcF
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8BG's original vision resonates with me strongly.  A computer made with off the shelf parts as much as possible so that the end user can completely understand the machine and also master it to bend it to the will.  It gives the user a tool for thinking, and learning and playing.  In this way it is in my mind superior to the Raspberry Pi, and for that reason the phase 3 X16 and the X8 don't hold so strong an appeal for me.  On the other hand, to each his own. 😉

Edited by Carl Gundel
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1 hour ago, Brad said:

That said, I have been following the project since it was first discussed on the Youtube video, and honestly the current X16 has an insane amount of feature creep.  ...

65816, 24bit address bus, directly addressable video RAM, system ROM in Bank 0, User ROM is Bank 1, dedicated dual serial chip, separate microcontroller to access the SD card, PSG with (a limited amount of) hardware ADSR ... there's been a substantial amount of feature pruning as well.

Even later, the Vera UART functions which had been added were stripped out to allow an increase in the addressed registers from eight to thirty-two.

And of course, features that were not pinned down could be seen as feature creep by someone who imagined something simpler and a clamp on features by someone who imagined something more ambitious.

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51 minutes ago, Carl Gundel said:

A computer made with off the shelf parts as much as possible so that the end user can completely understand the machine

I have never believed these are connected.  I think it is unfortunate that 8BG has been promoting this notion.

The only thing that makes off the shelf parts understandable is their documentation.  Without docs how could anyone design with them?  Even good docs stop at some level of abstraction.  For example, YM2151 docs describe nothing about its microarchitecture, which is need to really understand how it works.  I would argue that properly documented highly integrated designs can be more understandable than their off the shelf cousins.  Phase 1 X16 and Phase 3 X16 are equal complexity and equally understandable.  The packaging differences are superficial.

54 minutes ago, Carl Gundel said:

In this way it is in my mind superior to the Raspberry Pi, and for that reason the phase 3 X16 and the X8 don't hold so strong an appeal for me.

Raspberry Pi has no architectural commonalities with phase 3 X18/X8.  The only superficial thing they have in common is a high level of integration.

 

If people prefer the cool appearance of big PCBs with lots of chips, I have no argument with that.  I think they look cool too.  I just reject this idea that knowing this chip is the CPU and this chip does graphics imparts any meaningful knowledge of the computer's operation.

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29 minutes ago, picosecond said:

I have never believed these are connected.  I think it is unfortunate that 8BG has been promoting this notion.

The only thing that makes off the shelf parts understandable is their documentation.  Without docs how could anyone design with them?  Even good docs stop at some level of abstraction.  For example, YM2151 docs describe nothing about its microarchitecture, which is need to really understand how it works.  I would argue that properly documented highly integrated designs can be more understandable than their off the shelf cousins.  Phase 1 X16 and Phase 3 X16 are equal complexity and equally understandable.  The packaging differences are superficial.

Raspberry Pi has no architectural commonalities with phase 3 X18/X8.  The only superficial thing they have in common is a high level of integration.

 

If people prefer the cool appearance of big PCBs with lots of chips, I have no argument with that.  I think they look cool too.  I just reject this idea that knowing this chip is the CPU and this chip does graphics imparts any meaningful knowledge of the computer's operation.

I agree for the most part. The one place I think the big board with lots of chips wins is when trying to explain or teach it to people who have no idea. A concrete chip that can be described verbally is going to win out over a datasheet from a concrete vs abstraction perspective.

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2 minutes ago, Scott Robison said:

I agree for the most part. The one place I think the big board with lots of chips wins is when trying to explain or teach it to people who have no idea. A concrete chip that can be described verbally is going to win out over a datasheet from a concrete vs abstraction perspective.

Also for troubleshooting / maintenance, if a chip get fried it's easier to replace and certainly cheaper. I agree it's not going to happen a lot but who knows, playing with the hardware (expansion cards) can probably cause some issues 🤷‍♂️

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6 minutes ago, Scott Robison said:

I agree for the most part. The one place I think the big board with lots of chips wins is when trying to explain or teach it to people who have no idea. A concrete chip that can be described verbally is going to win out over a datasheet from a concrete vs abstraction perspective.

I get your point, but I would call what you are describing superficial understanding, not meaningful understanding.

The idea I am ranting against is that discrete implementations are necessary or superior for deep understanding.  That does not match my experience.  As an artistic choice, great.  As a pedagogical choice, not so much.

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46 minutes ago, picosecond said:

I have never believed these are connected.  I think it is unfortunate that 8BG has been promoting this notion.

The only thing that makes off the shelf parts understandable is their documentation.  Without docs how could anyone design with them?  Even good docs stop at some level of abstraction.  For example, YM2151 docs describe nothing about its microarchitecture, which is need to really understand how it works.  I would argue that properly documented highly integrated designs can be more understandable than their off the shelf cousins.  Phase 1 X16 and Phase 3 X16 are equal complexity and equally understandable.  The packaging differences are superficial.

Raspberry Pi has no architectural commonalities with phase 3 X18/X8.  The only superficial thing they have in common is a high level of integration.

 

If people prefer the cool appearance of big PCBs with lots of chips, I have no argument with that.  I think they look cool too.  I just reject this idea that knowing this chip is the CPU and this chip does graphics imparts any meaningful knowledge of the computer's operation.

Off the shelf parts (not programmable chips) have clearly defined functional boundaries and electrical interfaces.  This means each part is responsible for something.  The interaction between the chips is meaningful, and the circuit can be modified, customized, repaired, etc.  This is mostly sacrificed when all the functionality is simulated in a programmable chip.  The organization of the hardware can and does inform understanding of how the computer works, and simpler and more transparent design makes it easier to understand.  If none of this matters, then yes by all means let's just forget about phase 1 and 2 and go straight to FPGAs.  I'm not going to suggest that this makes the product pointless, but it's not at all what 8BG presented.

The Raspberry Pi is as you say highly integrated, and its operating system is Linux which is not ideal for personal mastery because of its size and complexity.  This can often be too much for the beginner or casual hobbyist.  The Raspberry Pi is a great product, don't get me wrong, but conceptually totally different from an X16.

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36 minutes ago, picosecond said:

The idea I am ranting against is that discrete implementations are necessary or superior for deep understanding.  That does not match my experience.  As an artistic choice, great.  As a pedagogical choice, not so much.

What group of students are we talking about, specifically? For a young kid, having individual components that can be visually segregated definitely helps. Once you hit a certain level of understanding abstraction, the physical representation is less important, but foundationally I think it's very useful.

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2 hours ago, BruceMcF said:

65816, 24bit address bus, directly addressable video RAM, system ROM in Bank 0, User ROM is Bank 1, dedicated dual serial chip, separate microcontroller to access the SD card, PSG with (a limited amount of) hardware ADSR ... there's been a substantial amount of feature pruning as well.

Even later, the Vera UART functions which had been added were stripped out to allow an increase in the addressed registers from eight to thirty-two.

And of course, features that were not pinned down could be seen as feature creep by someone who imagined something simpler and a clamp on features by someone who imagined something more ambitious.

Yeah, no dispute here...the waters have definitely been muddied as this project has proceeded, which is 100% like every single other engineering endeavor I've been a part of. Depends on which angle you're looking at it, I suppose.

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15 minutes ago, Carl Gundel said:

Off the shelf parts (not programmable chips) have clearly defined functional boundaries and electrical interfaces.  This means each part is responsible for something.  The interaction between the chips is meaningful, and the circuit can be modified, customized, repaired, etc.  This is mostly sacrificed when all the functionality is simulated in a programmable chip.

It feels like you are conflating microcontrollers and FPGAs.

Logic implemented in an FPGA has clearly defined functional boundaries and electrical interfaces.  Each part is responsible for something. Interaction between functional units are meaningful.  Given the necessary design collaterals the circuit can be modified or customized.

Some compiled C++ program which simulates a system is completely different of course.  But this has nothing to do with an FPGA implementation like CX8.

Sure, the 6502 core in CX8 won't have exactly the same microarch as one you bought from WDC.  The building blocks are different.  But they are not all that different.  The FPGA implementation is "just" a bunch of gates, flops and RAMs all wired together.

32 minutes ago, Carl Gundel said:

The Raspberry Pi is as you say highly integrated, and its operating system is Linux which is not ideal for personal mastery because of its size and complexity.  This can often be too much for the beginner or casual hobbyist.  The Raspberry Pi is a great product, don't get me wrong, but conceptually totally different from an X16.

I don't know what prompted this comment.  I never advocated for the Raspberry Pi here and specifically said it is a completely different architecture.

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44 minutes ago, picosecond said:

I get your point, but I would call what you are describing superficial understanding, not meaningful understanding.

The idea I am ranting against is that discrete implementations are necessary or superior for deep understanding.  That does not match my experience.  As an artistic choice, great.  As a pedagogical choice, not so much.

I agree, certainly the non-discrete components can be understood. From my perspective, I think of the big board with chips being easier to try to explain to my middle school computer class because there is a more concrete divide between chips rather than an all in one FPGA or SoC solution.

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28 minutes ago, picosecond said:

I don't know what prompted this comment.  I never advocated for the Raspberry Pi here and specifically said it is a completely different architecture.

That's true, sorry.  I think I was simply further making my case against the RPi vs the X16, which isn't clearly relevant to what you wrote.

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4 hours ago, picosecond said:

I just reject this idea that knowing this chip is the CPU and this chip does graphics imparts any meaningful knowledge of the computer's operation.

I disagree.

I've watched a bazillion repair videos, many of them arcade machine repairs. Many times, the failure mode tells you which of the chips is faulty - like if the even pixel rows of tiles are garbage but the odd rows are correct, that means probably the LSB of some logic chip has failed or is stuck hi/low. You can see how the computer does its machinations when the traces between the CPU and the RAM lead through decode logic.  Sure, on the INSIDE, this makes no difference whatsoever. STA $370c is going to make whatever's in the accumulator go to that address, regardless whether the entire transaction happens beneath an epoxy blob or if it heads out across copper traces and gets manipulated by a bunch of logic chips, splitting the bits up between a bunch of 1-bit DRAMS. You can capture these traces with an O-Scope or logic analyzer or whatever and see what's actually taking place. From the inside, the CPU says "STA $9F41" and you don't hear the FM playback change according to the value you just wrote - what now? What's broken? Not your code. Not the architecture. A real chip failed to place a value into another real chip or that other real chip failed to produce the expected output on a pin somewhere, or maybe it did and that signal didn't make it to the speaker jack.....

That's the difference. One's a "cyberspace" view of the architecture, and one's a "realspace" view of the architecture. You can say that you know the memory map of a computer system; that you know what the function of each and every memory-mapped register is. You can know exactly what the procedures are for communicating with devices at those addresses (or behind those addresses for things like VIA-attached stuff)... but that doesn't mean you know HOW the computer works. It just means you know how the computer WORKS.

See the difference?

 

Edited by ZeroByte
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I always wanted it to be a DIY kit and will absolutely prefer to consume it that way. To me this is simply good news.

I’m definitely more interested in the original X16 than the described X8. I mostly work with Zilog line CPUs and I’d prefer a single, full-featured X16 to serve as my single reference system for this CPU.

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5 hours ago, VincentF said:

Also for troubleshooting / maintenance, if a chip get fried it's easier to replace and certainly cheaper. 

Except for all the little bits that could be combined into a CPLD -- perhaps.

Edited by rje
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I didn't have strong opinions about the first two questions. I would probably buy an X8, though. When I first heard about the project I thought that $400-$500 would be a both realistic and reasonable price range. I would also consider contributing to crowdfunding.  A kit would do me no good. I've always sucked at soldering on a good day, and now I have what is probably permanent neuropathy in my fingertips.

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3 hours ago, rje said:

Except for all the little bits that could be combined into a CPLD -- perhaps.

Yes, the use of a CPLD in the X16c would be a compromise, because in the cost cutting version of a board, you have to compromise.

But if it functions identically to the X16p, I can understand it at the level of the circuit it is simulating, even if I may never understand it at the level of its VHDL specification and how the circuit optimizer turns that into a pattern of NANDs and NORs and latched bits.

8 hours ago, Brad said:

What group of students are we talking about, specifically? For a young kid, having individual components that can be visually segregated definitely helps. Once you hit a certain level of understanding abstraction, the physical representation is less important, but foundationally I think it's very useful.

What "students"? Sheesh, I'm a college Econ professor, how could I spend time on that in a class about the Great Depression and looking at the first two decade's worth of GDP value numbers?

My grandkids, of course!

In many cases, the "students" would be exactly the kind of interested beginners whose questions about what is the best 8bit computer to buy to explore 8bit computing was part of the original inspiration for this whole project.

Edited by BruceMcF
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18 hours ago, Brad said:

What group of students are we talking about, specifically? For a young kid, having individual components that can be visually segregated definitely helps. Once you hit a certain level of understanding abstraction, the physical representation is less important, but foundationally I think it's very useful.

Agreed.  It really depends on individual learning style, but generally speaking young people need things to be more concrete before they learn to see things in the abstract.

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12 hours ago, BruceMcF said:

But if it functions identically to the X16p, I can understand it at the level of the circuit it is simulating, even if I may never understand it at the level of its VHDL specification and how the circuit optimizer turns that into a pattern of NANDs and NORs and latched bits.

You know... his question got me to thinking about the relative value of 7400s versus CPLDs, and how different digital logic is today from back-when.   I guess there's still value in doing it with 7400s.

Edited by rje
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1 hour ago, rje said:

You know... his question got me to thinking about the relative value of 7400s versus CPLDs, and how different digital logic is today from back-when.   I guess there's still value in doing it with 7400s.

Heck, I see that the SD card SPI CS and the serial ROM SPI CS is side by side in a control register in the X8, and there might be one spare pin (if it isn't a pin stranded by lack of logic resources), and I'm like, "hey, that's a job for a 74x138, just send three bits out on pins undecoded, and you get 7 alternative SPI selects."

...

... OOH! WAIT! It might be possible to finesse away the need for a spare pin!

Use the next decoder! A 74x139 dual active low 2>4 decoder ... that's the ticket!

See, if you include a GPIO extender, you can use some of that GPIO for system uses. So you have one decoder, /EN tied to ground so it's always on, tied to the two pins that were original SD and serial flashROM CS's. So %01 SD card, %10 serial flash ROM %11 GPIO extender ... %00, SPI expansion bus.

Now, the other decoder has its two address pins tied to two of the GPIO (probably the top two, for convenience of addressing), and the active low for the first decoder's %00 tied to ITS /EN line. So you address the GPIO pin functions, set the top two pins to output, then address those pins as b0 and b1 and store the desired SPI slot number, 1, 2 or 3. The three four active low outputs go out on four of the pins on the 5x2 block header, plus MOSI, MISO, SCLK, +3.3v and GND. If there IS a spare pin, it can be used as an Alert pin, with a pull up resister, tied to the GPIO extender alert line and also brought in from a pin of the block pin header.

It's BETTER if there is a spare pin to be used for addressing, but it's still workable without ... to "turn off" the extension "slots", just set the GPIO selecting the extension slot to "slot 0", which is NC ... and it's probably a higher priority to use a spare pin for Alert if it's available.

Edited by BruceMcF
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2 hours ago, rje said:

You know... his question got me to thinking about the relative value of 7400s versus CPLDs, and how different digital logic is today from back-when.   I guess there's still value in doing it with 7400s.

In re-watching David's original dream computer video, he mentions that the VIC-20 was simple enough that a hobbyist could understand what every chip on the board does. I assume he didn't use the C-64 because it had a PAL to handle the address decoding complexity. I think that is driving the 74xx series vs. GAL/SPLD decision. While internally an SPLD is a very simple circuit, the implementation is still hidden from you.

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Just now, Wavicle said:

In re-watching David's original dream computer video, he mentions that the VIC-20 was simple enough that a hobbyist could understand what every chip on the board does. I assume he didn't use the C-64 because it had a PAL to handle the address decoding complexity. I think that is driving the 74xx series vs. GAL/SPLD decision. While internally an SPLD is a very simple circuit, the implementation is still hidden from you.

This is why I want to create a dream computer made with vacuum tubes. Transistors are just too dang magical. 😄

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