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What is VERA - physically?


TomXP411
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I know this has been answered somewhere else, but the information has been buried beneath a mountain of other comments. 

@Frank van den Hoef

Can  you talk about the FPGA that's actually being used for VERA? 

All this talk about FPGAs and what can and can't be done has got me itching to know more - and possibly to do a deep dive into the technology, myself. 

 

 

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On 10/12/2021 at 7:06 PM, TomXP411 said:

FPGA that's actually being used for VERA

Lattice ICE40UP5K in the 48-pin QFN. https://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus

The datasheet: https://www.latticesemi.com/view_document?document_id=51968

Lattice's iCE40 family is a good place to start exploring FPGAs.  They are a good deal simpler than most offerings from Xilinx and Intel.

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If I would treat VERA as a black box, how is it accessed from outside (the 6502 CPU)? Does it have a couple of address input and 8 bit data in/output pins that are connected just like RAM or RAM to the bus of the CPU?

How this internally works? Do some FPGA already have some processor built-in or are there standard libraries available for the FPGA-programming software that "wire" certain virtual processors inside the FPGA?

Do I understand it from the datasheet correctly, that level shifters are needed to communicate with a 5V bus because it operates at 1.2V?

Edited by Ju+Te
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On 10/13/2021 at 12:43 PM, Ju+Te said:

If I would treat VERA as a black box, how is it accessed from outside (the 6502 CPU)? Does it have a couple of address input and 8 bit data in/output pins that are connected just like RAM or RAM to the bus of the CPU?

How this internally works? Do some FPGA already have some processor built-in or are there standard libraries available for the FPGA-programming software that "wire" certain virtual processors inside the FPGA?

Do I understand it from the datasheet correctly, that level shifters are needed to communicate with a 5V bus because it operates at 1.2V?

There are different FPGA with differing capabilities. Not all are such low power, though mostly I think yes, you would need level shifters to interact with a 5V bus.

For communication between a physical CPU and the FPGA (or really, anything interacting with the FPGA), your HDL defines a number of externally exposed IO lines to serve whatever purpose you want. For example, I have a Nexys 4 DDR board that exposes 40 pins to the outside world (and more IO is assigned to other IO devices on the board itself, such as switches, 7 segment displays, LEDs, network, VGA, etc, etc, etc).

Some FPGA have a CPU sitting next to the FPGA, or IP is available to embed a soft core CPU into the fabric of the FPGA. Others just provide the FPGA and a processor (if desired) has to be created from scratch or sourced from another project or offering.

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On 10/13/2021 at 2:43 PM, Ju+Te said:

If I would treat VERA as a black box, how is it accessed from outside (the 6502 CPU)? Does it have a couple of address input and 8 bit data in/output pins that are connected just like RAM or RAM to the bus of the CPU?

Pretty much.  I don't remember seeing the interface details published, but it should be similar to a 65C22 VIA.

On 10/13/2021 at 2:43 PM, Ju+Te said:

How this internally works?

It's a bespoke digital design.  The logic building blocks inside the ICE40UP5K are pretty simple, mostly D flip-flops in various flavors and 4-input look-up table cells which can do any arbitrary 4-bit logic function.  The full cell library is specified here: https://www.latticesemi.com/view_document?document_id=52206

On 10/13/2021 at 2:43 PM, Ju+Te said:

Do I understand it from the datasheet correctly, that level shifters are needed to communicate with a 5V bus because it operates at 1.2V?

Almost.  1.2V is the core voltage.  There is a second power rail for the IO, 3.3V for Vera.  The FPGA has internal level shifters between the core and IO rails.  External level shifters are needed to interface the 3.3V Vera IO to the 5V X16 logic.

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On 10/13/2021 at 2:43 PM, Ju+Te said:

If I would treat VERA as a black box, how is it accessed from outside (the 6502 CPU)? Does it have a couple of address input and 8 bit data in/output pins that are connected just like RAM or RAM to the bus of the CPU? ...

From what they've said before, exactly ... 8 I/O pins connect to the data bus, 5 I/O pins connect to A0-A4, and from that I would guess three more pins allocated for chip select, R/W and PHI2, with all the lines from the 6502 level shifted to 3.3V.

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On 10/13/2021 at 5:16 PM, BruceMcF said:

From what they've said before, exactly ... 8 I/O pins connect to the data bus, 5 I/O pins connect to A0-A4, and from that I would guess three more pins allocated for chip select, R/W and PHI2, with all the lines from the 6502 level shifted to 3.3V.

I think the same thing. More than that would mean a lesson in 65x logic design, which could be a thread all of its own. 😃

 

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On 10/14/2021 at 12:53 AM, TomXP411 said:

I think the same thing. More than that would mean a lesson in 65x logic design, which could be a thread all of its own. 😃

One interesting point is whether it's timing as designed will play nice with a 16MHz Z80 bus, since a 32byte register address range fits well with the 256byte I/O address space of the Z80. Use a 2->4 decoder to select Vera on I/O (a6,a7)=%00, select tri-state hex latches on %01 and %10, tie the Vera SPI select to the output enable of the %01 latch to select from four SPI devices, tie the other latch to select a 32K memory bank on a 512KB SRAM, and it could make a really cute little CP/M Plus system to play with ... two SD cards, one UART and an I2C bus master for parallel port, keyboard, etc.

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On 10/14/2021 at 8:16 AM, BruceMcF said:

One interesting point is whether it's timing as designed will play nice with a 16MHz Z80 bus, since a 32byte register address range fits well with the 256byte I/O address space of the Z80. Use a 2->4 decoder to select Vera on I/O (a6,a7)=%00, select tri-state hex latches on %01 and %10, tie the Vera SPI select to the output enable of the %01 latch to select from four SPI devices, tie the other latch to select a 32K memory bank on a 512KB SRAM, and it could make a really cute little CP/M Plus system to play with ... two SD cards, one UART and an I2C bus master for parallel port, keyboard, etc.

If I recall, the system clock is also driven by VERA. In that case, there would be firmware changes needed for VERA to live on an 8080 style system. Either VERA would need to generate the clock, or you'd have to drive the I/O side independently from the GPU side of the core. In either event, you might as well modify the bus sequencing to account for 8080 style I/O while you're at it. 

 

 

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On 10/14/2021 at 3:33 PM, TomXP411 said:

If I recall, the system clock is also driven by VERA. ...

I had once been under that impression, but AFAIU, no, the system clock is on the board, and the bus interface is not synchronized with the internal Vera clock.

I believe that driving the system clock from a countdown from the internal FPGA clock may have been one idea for handling the problems with interference between bus interface they added to the Gameduino and the actions of the J1 coprocessor that the Gameduino included, but that since Vera doesn't have an embedded processor core, it doesn't have the same problem.

Edited by BruceMcF
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On 10/14/2021 at 1:33 PM, TomXP411 said:

If I recall, the system clock is also driven by VERA. In that case, there would be firmware changes needed for VERA to live on an 8080 style system. Either VERA would need to generate the clock, or you'd have to drive the I/O side independently from the GPU side of the core. In either event, you might as well modify the bus sequencing to account for 8080 style I/O while you're at it. 

 

 

This is incorrect. The VERA is designed so that it’s buss interface is independent of the host clock because we want it to work on other systems. It does not generate the system clock. 

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On 10/19/2021 at 1:41 PM, Lorin Millsap said:

This is incorrect. The VERA is designed so that it’s buss interface is independent of the host clock because we want it to work on other systems. It does not generate the system clock. 

Thanks. I know I remembered some  conversation about that, but it might have been one of those passing "this is what we're thinking of doing" things. 

 

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On 10/19/2021 at 5:31 PM, TomXP411 said:

Thanks. I know I remembered some  conversation about that, but it might have been one of those passing "this is what we're thinking of doing" things.

As I mentioned, it may have been a proposal ... and quite possibly not from the design team ... to deal with a Gameduino problem that simply doesn't exist with Vera, as Vera has no embedded co-processor core. That would have been almost near the end of the "Gameduino video display era".

That discussion would have been long before this site was built, so it would be lost in the morass that is the FB discussion system.

h/t @Lorin Millsap for confirming that the Vera "register" access is not synchronous with the Vera VGA dot clock.

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