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VERA PCM FIFO_empty flag



Is there room left in the VERA firmware / resources to make bit 6 of the VERA_audio_ctrl register into a read-only bit which is set if FIFO is currently empty, clear if not? If making it read/write takes less resources, then it could also be a "clear FIFO" signal if set during a write, just like bit 7.

If you want to keep the digital audio latency as low as possible, then it would be helpful to know if the FIFO is completely empty so that you can take measures to prevent buffer underflow going forward. Currently, you can only know if the FIFO is full or if it's "low" which has different levels of urgency depending on the sample rate being used. 8K mono 8bit can have 7 frames' worth of data (128ms) in the "low" state whereas high-quality audio cannot even fit more than a single frame's worth in the entire 4K FIFO. Given the sheer size of PCM data streams, I expect it's likely that many programs will use the lowest quality settings that produce acceptable-sounding audio.

Using a FIFO strategy that favors keeping it full does present challenges where latency is concerned. At lower sample rates, it could become fairly noticeable that the end of the previous sample was cut off if you're forced to empty the FIFO in order to change bit depths, stereo, etc.

Maybe I'm over-thinking things and chopping off the ends of digital clips isn't such a big deal, and I should just go with aggressive FIFO filling, but if it's feasible to add this bit to the CTRL register, it would be quite useful.

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