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BruceMcF

Retro CP/M (with the CX16 and otherwise)

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It should be obvious I am not a hardware hand ... where I say HA & LA "latches" above, if they are D latches, or bus transceivers with D latch functions, they will float with the new data on PA of the User Port when the mode moves from /HALE to /LALE to /W. They need to be flip-flops, to latch the data on the falling or rising edge of /HALE | /LALE, hold it until the next /HALE or /LALE,  and put it on the SRAM address lines whenever /BUSREQ is low.

OTOH whether the flip flops latch their data on the rising edge or falling edge latch might be down to price / availability of through hole parts for bread boarding. The only difference is write the address byte into PA THEN assert the mode with falling edge, assert the mode then write the address byte into PA with rising edge, so whichever one it is will determine the byte writing protocol. But either way, writing a sector will be a "DEC PB / INC PB" process for generating the mode.

Also, the Z80 /BUSACK obviously cannot be connected to /SELRAM, it has to go through a driver (74x373 are a good general purpose bus transceiver / latch), since when the /BUSREQ cycle is over it will be driven high by the Z80, and direct connect would contend with the /MREQ that normally provides /SELRAM. So make it 3 Main IC's, 2 flipflops, 1 LD & 1 dual 2-4 decoder (eg. 74x139), or a 7IC CP/M board.

An advantage of the Z80 multiple clock cycle memory access process is that it looks like 55ns should be fine for a 16MHz Z80. Unlike the 65xx memory cycle, both read and write states are asserted for MORE than one full clock cycle ... & +5v through hole 16MHz clock modules are inexpensive and still readily available. Though I would probably start breadboarding at 8MHz and then try faster clock modules at 2MHz intervals until I find out which one is too fast.

Edited by BruceMcF

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Of course, the ultimate goal includes direct C64 User Port access.
But the C64 User Port doesn't have as much GPIO. We've got Port B, PA2, /FLAG2, /PC2, and the two serial ports and their counters.

Given a CP/M card that plugs directly into the CX16 User Port block header, the cleanest is to create Port A on the User Port card using the serial ports and serial shift registers ... one Parallel In, Serial Out, one Serial In, parallel Out. That takes 16 clock cycles to transfer a byte, but:
1] For Z80->UP, the system can be set up to start a single shot byte load as soon as the /ALERT is generated, and we have two additional PortB lines, so if the server is doing something, when it polls the /ALERT line and then checks if the byte is loaded, quite often it would be, and if not it would only need one or two busy loops to retrieve it.
2] For UP->Z80 when /BUSREQ is asserted, in a loop:
- DEC PortB : INY : STY SerialOut : LDA (SRC),Y : NOP : NOP : NOP : INC PortB : STA SerialOut : NOP : NOP : NOP : CPY N : BNE -
... would be about enough spacing to handle it, which is still a lot faster than the fastest UART transfer a C64 can handle without a serial cart.

A CX16 expansion card version to avoid hogging the User Port GPIO might be two VIA's on a card, the first VIA driving a User Port compatible Parallel Port, the second VIA controlling the CP/M card as a block header daughterboard, and the two serial shift registers plus PB6&PB7 as four additional GPIO providing a UART or RS-232C serial port.

Mind, that expansion card would not be dedicated to hosting a CP/M card, it would be a second User Port for essentially any use of the first User Port.

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On 7/9/2020 at 12:15 PM, BruceMcF said:

So that's level 1 ... next post, level 3, the "CP/M card" like the Apple II card or the not always functional C64 CP/M cartridge.

Love the idea of making it possible to run CP/M on the X16!

Used to have a Microsoft Z80 SoftCard for my Apple computer to be able to run CP/M and software not native to 6502/DOS3x/ProDOS.

Classic:

332e0d606926d8b2fca0505fdf4220a8.jpg

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I am also much more enthusiastic about having it than making it ... but I am enthusiastic ENOUGH about having it that I may make a trip to Shenzhen in the gap between the two week Chinese New Year holiday and the start of semester to see about getting it made if nobody else is game.

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