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General Projects Involving VERA


Kalvan
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On 6/2/2022 at 11:15 AM, svenvandevelde said:

I fully agree. An alpha of 2 bits would already be more than sufficient. 0%, 33%, 66%, 100% would do! Or 3 bits, as you said. So that a fire ball looks like a fireball in a complex scene, and not like a painted clodder of color. (Exagerating a bit). And with that 2 bits would be available for other purposes.

The other part is the memory ... 128K. It is great fun trying to fit all into the vram (that''s why i've built a VRAM memory manager), to dynamically skip in and out sprites and tiles during game flow, but it kind of limits the scene ... 256K would be better: more sprites, one full 640x400 bitmap in 256 color palette, sprites in 256 colors would become an option etc. Was there a reason why there is a limit of 128K?

 

The iCE40UP5K has 128K of SRAM on the die. It's an usual feature in a $6 FPGA (now $9, thanks to the chip shortage); normally a design would go off-chip to a dedicated SRAM IC, but by using this FPGA that was not necessary. This keeps costs down but also limits expansion since there are no available IOs to interface with an external high speed SRAM component.

128K is double the addressable memory of the 6502 so it feels to me like it is sized right for the intended product. Even at 8MHz, writing a 320x240x8bpp bitmap to VERA is already a fairly slow affair.

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On 6/3/2022 at 2:04 AM, Wavicle said:

It's an usual feature in a $6 FPGA (now $9, thanks to the chip shortage); normally a design would go off-chip to a dedicated SRAM IC, but by using this FPGA that was not necessary.

This is an explanation I understand. So it was cost. Makes sense. Anyway, as I said, the 128K makes a nice challenge for programmers to use the vram efficient :-).

image.png.c12fc1e54d19ef67efaed685b0e1fe14.png

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On 6/3/2022 at 11:28 PM, svenvandevelde said:

This is an explanation I understand. So it was cost. Makes sense. Anyway, as I said, the 128K makes a nice challenge for programmers to use the vram efficient :-).

128K is decadent in comparison to a 16K VIC II bank. 🙂

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For reference, here is a BOM I worked out for a single VERA (except for the PCB which is prohibitively expensive to buy a single unit, but the price comes down quickly in bulk, so I priced it as 1/15th of a 5 panel, 15 board order) using prices as of today at Mouser: VERA_BOM_2022_Jun_05.tsv (github.com).  I know this is a project with international appeal, but to simplify on my end, all prices are in $USD.

Base board (voltage regulators; bus interface; FPGA; clock; passives): $23.12

VGA: $2.85

Composite + S-Video: $5.15

PSG Audio: $3.52

SD Card: $3.09

Total part cost: $37.73 + tax + shipping. Does not include assembly, test, yield loss and things like that.

Using bulk pricing of ICs in 10-24 unit quantities and passives in 100-249 unit quantities, total part cost is $30.14 (+tax +shipping).

Now, if we circle back to the question of what would it take to get more VRAM, a larger FPGA would add about $10 and external VRAM would be about $8 for 512K (~$6 for 256K).

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On 6/5/2022 at 11:44 PM, Wavicle said:

Now, if we circle back to the question of what would it take to get more VRAM, a larger FPGA would add about $10 and external VRAM would be about $8 for 512K (~$6 for 256K).

$6 to $8? That's it? Seriously? I would have gone for the 256K then when designing the cx16. Video capabilities boost platform popularity. I mean, the difference is only a few bucks additionally. I had understood moving to a VRAM larger than 128K would be a + $50 cost or something. 

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On 6/5/2022 at 7:18 PM, svenvandevelde said:

$6 to $8? That's it? Seriously? I would have gone for the 256K then when designing the cx16. Video capabilities boost platform popularity. I mean, the difference is only a few bucks additionally. I had understood moving to a VRAM larger than 128K would be a + $50 cost or something. 

$6-$8 for SRAM + $10 for the FPGA with more IOs + shipping + tax + additional development time. The increase in part cost does not usually represent the cost increase to the end user cost. Factors such as yield, R&D cost, and profit have to be factored in as well. Increasing the VRAM is going to increase the total cost of the VERA board by at least 50%. For a point of reference, I have two assembled, tested, and working VERA boards and most of the parts I need to build 8 more (just need to order new PCBs because the SD card socket is no longer available). Even though my part cost per finished board is around $27, my total outlay to get here is close to $500 - just for VERA. (I'm in for about another $800 on the parts used to build my X16 on the breadboard.) Hardware development is expensive (but fun, so there's that).

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Also consider that they're not going to be buying these one at a time. It's going to be in bulk purchases, where the $6 to jump to a 256K RAM unit gets multiplied by at least 100, maybe more. That adds up quickly.

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On 6/6/2022 at 2:05 AM, Wavicle said:

$6-$8 for SRAM + $10 for the FPGA with more IOs + shipping + tax + additional development time. ...

Quite. "$10 more for an FPGA that can use external SRAM and $6-$8 for the SRAM" means $6 versus $22-$24, for a system with a CPU that is $10 q1 at Mouser ($6 q1000).

It seems like the POINT of the FPGA in the Vera is to support designs where the amount of RAM available as Block RAM in most inexpensive commodity FPGA's is not quite enough, but to save the cost of supporting enough I/O pins to allow access to a RAM of that size.

And remembering how the project started with the Gameduino version 1.0, with its 32K of visual space being very constraining, Vera is kind of right in the strike zone.

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