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X16 Emulator with real VERA display


Wavicle
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I got my Raspberry Pi 3B+ to drive the VERAduino using an MCP23017 I2C GPIO expander.

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Then thought to myself that if I were sufficiently clever, I could redirect all of the emulator's traffic to its emulated VERA out to the real VERA on the protoboard. A hundred or so lines of code later and now I have everything emulated except for VERA:

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Colors are a little off; I think that I need to double check all of my DAC wiring because it looks like I may have some bits swapped. Ignore the missing text on the left, this monitor likes to cut off the first 30 or 40 VGA pixels for some reason. But there it is! A bit slow because the I2C is pegged at 400kHz; I am ordering an SPI GPIO expander (MCP23S18) to see if I can't improve that some.

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On 4/1/2022 at 5:25 AM, TomXP411 said:

That's impressive!  

So dumb question: can you build I2C into the FPGA and skip the I/O expander?

 

You absolutely could. It would run faster too since you would not have simulate a real data bus with it. A better option would be to build SPI into the FPGA since you can easily run it 20-30x faster than I2C. That's what the Gameduino did. In this case I want to keep the VERA bus interface as is, but I do have another UPduino...

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On 4/1/2022 at 12:35 PM, Wavicle said:

You absolutely could. It would run faster too since you would not have simulate a real data bus with it. A better option would be to build SPI into the FPGA since you can easily run it 20-30x faster than I2C. That's what the Gameduino did. In this case I want to keep the VERA bus interface as is, but I do have another UPduino...

Quite ... indeed, without the 8 data lines, 5 address lines and whatever else is there ... /CS and R/W? ... you could have 1 slave SPI as a replacement for the 6502 bus interface and still have I/O for additional select lines for the existing master SPI. For the slave SPI, one control byte with the bottom five bits referring to the bus register and three bits for operation. One bit for read/write leaves four modes available ... %00 could be single byte, %01 could be two byes to consecutive registers (not useful for all registers, but there are some register pairs where it is useful), %10 could be multiple bytes up to a page to a single register location.

Maybe %11 could be a two-line serial input similar to the two-line serial output available from some flash serial SPI chips, where in the two-line flash serial MISO turns into, in effect, MISO_bit1 and MOSI turns into MISO_bit0 for the bit pair (remembering that SPI bits are big endian, so the "normal" one is the "first" bit in the pair) ...

... actually, come to think of it, if you have MOSI turn MOSI_bit0 and MISO turn into MOSI_bit1, then maybe with circuitry that can suppress the serial clock to the flash serial connection (driven by an additional microprocessor GPIO), you could select the flash serial, set it up, pause its clock, select Vera, set it up, then float the microprocessor MISO/MOSI lines and load dummy data into the microprocessor SPI port to run the serial clock to let the flash serial load a page directly into Vera at double the SPI clock bit rate.

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