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StinkerB06

Some VERA questions

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@Frank van den Hoef

  1. What would happen if a DC START register is greater or equal to its matching STOP register? Will it flip the image or not render it at all? Flipping would make the VERA's logic design a bit more complicated, so I assume it's the latter.
  2. Does a sprite with a lower Z-depth value and lower position in memory actually render behind a sprite with higher Z-depth and position, or will it display garbage like the GBA? (E.g. sprite 0 has Z=2, sprite 1 has Z=3) Note that lower positions mean higher-priority sprites if their Z-depth is the same.
  3. Will the PSG's noise wave use a predefined sequence? The emulator's PSG code doesn't seem to implement one, and just takes a random number from 0 to 63. Maybe it uses a true-random supply from somewhere in your FPGA?

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It would be great if someone with intimate knowledge of vera can answer what the "correct" behaviour is, but in the meantime the emulator purportedly has nearly cycle accurate emulation of the graphics hardware so you should be able to assume that what you see in the emulator is what you'll get on real hardware

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Having asked after a number of the VERA's features in the past... as best as I can tell, without having a physical VERA in my hot little hands, the DC start/stop registers are accurate to hardware, and the sprite drawing is also accurate to hardware.

I have no doubt that the PSG noise function will be different from the emulator's implementation, as the emulator uses `rand() & 63` as an approximation. I expect this reflects the bit accuracy of the VERA, and will be similar, but will not perfectly agree with the exact sequencing of the VERA. I appreciate that different noise implementations will have a different color and texture to them, but without knowing the exact method of the VERA, it's not possible to perfectly replicate this behavior.

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20 minutes ago, StephenHorn said:

I have no doubt that the PSG noise function will be different from the emulator's implementation, as the emulator uses `rand() & 63` as an approximation. I expect this reflects the bit accuracy of the VERA, and will be similar, but will not perfectly agree with the exact sequencing of the VERA. I appreciate that different noise implementations will have a different color and texture to them, but without knowing the exact method of the VERA, it's not possible to perfectly replicate this behavior.

Not to get too off topic, but just a point that the YM2151 emulation is also an approximation, especially when it comes to that noise generator as well. As Frank has been developing both the VERA VHDL and emulation code, that the graphics part are going to be very close, if not exact, but also very dependent on host performance. I've run the emulator on some absurdly beefy machines, and nothing is able to run at 100% all the time.

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1. If the horizontal pixel counter equals DC_START the output will be enabled, at DC_STOP it will be disabled. So if DC_START is bigger than DC_STOP, DC_STOP is basically ignored and the image will be displayed up to the end of the line.

2. Sprites are rendered in order of their index, so higher index sprites will be rendered in front of lower index sprites, except when it has a lower Z-value.   No garbage will occur.

3. On the real hardware, the noise generation is done using a LFSR. It could be emulated, but I think the rand is doing a quite similar job. 

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On 7/26/2020 at 12:40 AM, Frank van den Hoef said:

3. On the real hardware, the noise generation is done using a LFSR. It could be emulated, but I think the rand is doing a quite similar job. 

Some time ago, I was playing with LFSR combinations in my spare time. If the noise waveform will be using an LFSR, what will the bit-length be and what taps will it use?

From what I understand, many consoles used only one XOR (or two bits tapped) for whatever reason, and the repetitive nature of the noise becomes apparent the shorter the sequence and when only one XOR is used. And the SID chip's noise length was impressively long! 😮 

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3 hours ago, BTTFdude said:

Some time ago, I was playing with LFSR combinations in my spare time. If the noise waveform will be using an LFSR, what will the bit-length be and what taps will it use?

From what I understand, many consoles used only one XOR (or two bits tapped) for whatever reason, and the repetitive nature of the noise becomes apparent the shorter the sequence and when only one XOR is used. And the SID chip's noise length was impressively long! 😮 

And if the sequence length is very short, it actually produces an audible tone, hence the "periodic" noise mode found in some sound chips.

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