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Banking on the Mega65?


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No, it's quite different. The Mega65, like the original Commodore 65 design, banks out the entire 64k memory space. Bank 0 is like a regular C64, and provides backward compatibility. Other banks have additional RAM and ROM. The C65 had another 64k of RAM in bank 1, then 128k of ROM across banks 2 and 3. The Mega65 has all this, but it also has the option to make that ROM into RAM (which it actually is, just merely made write-protected while in C65 compatibility mode). The remaining 12 banks are all RAM, if you have it populated. So, you can have up to 1MB of RAM, or more that apparently can be swapped out.

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On 6/6/2022 at 7:19 AM, SlithyMatt said:

No, it's quite different. The Mega65, like the original Commodore 65 design, banks out the entire 64k memory space. Bank 0 is like a regular C64, and provides backward compatibility. Other banks have additional RAM and ROM. The C65 had another 64k of RAM in bank 1, then 128k of ROM across banks 2 and 3. The Mega65 has all this, but it also has the option to make that ROM into RAM (which it actually is, just merely made write-protected while in C65 compatibility mode). The remaining 12 banks are all RAM, if you have it populated. So, you can have up to 1MB of RAM, or more that apparently can be swapped out.

Mega65 has the "backward compatibility" with what the C65 seemed to be attempting (realizing we have no idea what the end product would have been since there was no end product). In addition to the 20 bit address space of the C65, Mega65 actually has a 28 bit address space, allowing it to access up to 256 MB of data, and it has some extended instructions that allow direct access to that complete address space (though large parts of it are marked reserved for future use). So not only is Mega65 banking different than CX16, its even different (extended) beyond what C128 and C65 did / would have done.

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On 6/6/2022 at 7:42 AM, Scott Robison said:

Mega65 has the "backward compatibility" with what the C65 seemed to be attempting (realizing we have no idea what the end product would have been since there was no end product). In addition to the 20 bit address space of the C65, Mega65 actually has a 28 bit address space, allowing it to access up to 256 MB of data, and it has some extended instructions that allow direct access to that complete address space (though large parts of it are marked reserved for future use). So not only is Mega65 banking different than CX16, its even different (extended) beyond what C128 and C65 did / would have done.

Here's something about the original C65 CPU.  

https://en.wikipedia.org/wiki/CSG_65CE02

Some differnces from the 6502:

  • "B" register: Base Page. Relocates "Zero Page" to anywhere in memory. (Similar to but slightly different than the 65816.)
  • 16-bit stack register, so the stack can be up to 64K
  • Z index register. 
  • BRA (Branch Always) and BSR: basically faster jump and jump to subroutine instructions
  • 16-bit relative addressing. This should make code relocatable
  • "word' instructions, which allow for 16-bit data operations

I don't see instructions for a wider address bus in this article, so I'm thinking this was done with the MMU that was embedded in the CSG 4510 package. 

 

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On 6/6/2022 at 12:07 PM, TomXP411 said:

I don't see instructions for a wider address bus in this article, so I'm thinking this was done with the MMU that was embedded in the CSG 4510 package. 

Correct. Much as with the MMU on the C128, the CPU only ever has a 64K window into memory, so you have to get creative with banking. One exception being that there is a address mode for extended instructions to access anything in the 28 bit address space, but that's really only useful for register manipulation as PC is still a 16 bit register.

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