Splitting clock signal - 6502

[Bader 11]

Hello

Just got a 6502 A in the mail which I understand runs at 2MHz. I don't have any of those  crystal oscillators, but I do have a 4MHz. Can I split the signal using logic gates? At the top of my head perhaps an XOR gate and a D-latch set/reset latch should do it? But the details are not the point, the question is, is it viable or would it not be exact enough?

 

Thanks

Edited October 16 by Bader

[StephenHorn 228]

I don't have time to find the exact location of his solution, but didn't Ben Eater do some kind of clock division for his homebrew VGA circuit?

[Bader 11]

oh I'll have a look, thanks

[EMwhite 38]

There is also this: 

 

He is no Ben Eater (not quite as organized, rehearsed, etc.) but based on his clock starting point, he appears to have based his design on Ben's original clock.  I've got clock dividers in my modular synthesizer that work in very much the same manner.  The shape of the signal (that the presenter struggles with) ultimately causes issues with the ICs dependent on clock but I think below a given # of single digit Mhz. you are probably ok and will need to try it.

 

[Bader 11]

Been playing around in Logisim. To halve the frequency, don't I really just need a D-latch with the invertered Q going to the enable (or is it called input) pin? Like I've done in the picture? I don't really need to split the signal, just remove half the ticks.

[StephenHorn 228]

Seems like that would work, sure.

[Bader 11]

awesome, thanks all!

[Bader 11]

update, if anyone is curious

Not getting it to work. I've come as far  as making the outputs do as I want as long as I don't use not Q as input. When I do use not Q then switchover seems random. My guess is I have to de-bounce it but I really have no idea. Will continue experimenting when I'm closer to sobriety

[StephenHorn 228]

6 hours ago, Bader said:

update, if anyone is curious

Not getting it to work. I've come as far  as making the outputs do as I want as long as I don't use not Q as input. When I do use not Q then switchover seems random. My guess is I have to de-bounce it but I really have no idea. Will continue experimenting when I'm closer to sobriety

Not to ask silly questions, but is there a timing graph for the component you're using, and do you know whether your clock input is conforming to the latch's requirements?

[JimmyDansbo 55]

In theory, it should work. I have just tested in Logisim as well, both the buil-in d-latch and one made from NAND gates seems to be able to divide the clock signal.

As StephenHorn says, ensure that your chip(s) can handle the signal they receive. (dig in to the datasheets).

[Bader 11]

10 hours ago, StephenHorn said:

Not to ask silly questions, but is there a timing graph for the component you're using, and do you know whether your clock input is conforming to the latch's requirements?

Not silly at all as I am completely new to this and that hadn't occurred to me. Shall have a look thanks

[Bader 11]

3 hours ago, JimmyDansbo said:

In theory, it should work. I have just tested in Logisim as well, both the buil-in d-latch and one made from NAND gates seems to be able to divide the clock signal.

As StephenHorn says, ensure that your chip(s) can handle the signal they receive. (dig in to the datasheets).

I built with NOR and AND as in the Ben Eater videos. Will try this one as well

[JimmyDansbo 55]

You could also have a look at how the 74ls74 is built. It may very well be a better design.

https://www.ti.com/lit/ds/symlink/sn74ls74a.pdf

The 74ls74 seems to be edge triggered without using the strange NOT-NOT-NOT-AND circuit I have above.

[BruceMcF 155]

Simple D-type divide by 2 circuits have problems if the clock edges are not sharp enough. Feeding the clock through an inverter might sharpen its edges.

[Bader 11]

3 hours ago, BruceMcF said:

Simple D-type divide by 2 circuits have problems if the clock edges are not sharp enough. Feeding the clock through an inverter might sharpen its edges.

thanks, will give all of these a try once manage to free up some time

 

[Bader 11]

The result of using a 74LS74 (D flip flop) and  a 74HCU04 (hex inverter) is going from this:

 

 

To this:

 

And it's probably going to get a bit better once I tied down all unused inputs as well, cheers everyone!

[StephenHorn 228]

Holy smokes, no wonder your latch was having problems. That original signal isn't a square wave clock signal--- it's a bleedin' triangle wave! Was that really the output from a crystal oscillator?

Edit: I may be dumb or simply inexperienced, I thought crystal oscillators produced square-ish signals.

Edited November 11 by StephenHorn

[Bader 11]

Here's the circuit

 

This is the tutorial I followed:

I've since found other ones that also uses inverters but I didn't have all the component values for those. I might try some other ones as well
 

[Bader 11]

Interestingly enough, if I put even a 6Mhz, or faster, crystal in instead, it doesn't work very well at all. I was lucky that I found a tutorial using components that matches the speeds I wanted to run I guess. There certainly is lots to learn here