Looks like VERA could be undated to be a fast stack.
When using Data0 and Data1 registers there is a separate pointer for each register.
Could you have a VERA "stack" mode where the registers use the same pointer?
Thus, a data store to Data0 would be a push, and a data load from Data1 would be a pull.
With this setup the program would not need to keep track of a stack pointer - let VERA keep track.
A "load then read" combination would only take one cycle more than the standard "PHA PLA" combination and
would allow a much larger stack.
For users of a 65816 there would be no real advantage, but for 65C02 users the increased stack size might be useful.
VERA fast stack implementation
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Ed Minchau
- Posts: 483
- Joined: Sat Jul 11, 2020 3:30 pm
Re: VERA fast stack implementation
The only problem with that is keeping track of where you are if you need to use Data0 or Data1 for something else.
I did something similar for the audio on the video demos I've done, since MACPTR doesn't allow direct loading to the PCM buffer. I would just load the audio clip (about 1/10th of a second) into VERA RAM using MACPTR, and then treat it as a FIFO buffer to push data to PCM audio.
I did something similar for the audio on the video demos I've done, since MACPTR doesn't allow direct loading to the PCM buffer. I would just load the audio clip (about 1/10th of a second) into VERA RAM using MACPTR, and then treat it as a FIFO buffer to push data to PCM audio.
Re: VERA fast stack implementation
There are actually at least two problems with this idea.
One of them is keeping track of data port addresses, as Ed already mentioned.
The other is: since DATA0 and DATA1 have separate address registers, pushing more than one byte to this "stack" would require you to set the read address every time you want to pop values from the stack and vice versa. For example, if you push three bytes to the stack, DATA0 address would go up (or down?) by 3. DATA1 address wouldn't change, so if you wanted to pop some values, you'd first have to set it to the correct value (DATA0 address +/-1).
It would actually be simpler to use only one data port and toggle its direction bit when you want to switch between pushing and popping. And also add/subtract 1 from that address because VERA updates the address after both read and write, while the CPU first writes then updates the stack pointer on push, but on pop it does the things in reverse (update pointer first, then read)
One of them is keeping track of data port addresses, as Ed already mentioned.
The other is: since DATA0 and DATA1 have separate address registers, pushing more than one byte to this "stack" would require you to set the read address every time you want to pop values from the stack and vice versa. For example, if you push three bytes to the stack, DATA0 address would go up (or down?) by 3. DATA1 address wouldn't change, so if you wanted to pop some values, you'd first have to set it to the correct value (DATA0 address +/-1).
It would actually be simpler to use only one data port and toggle its direction bit when you want to switch between pushing and popping. And also add/subtract 1 from that address because VERA updates the address after both read and write, while the CPU first writes then updates the stack pointer on push, but on pop it does the things in reverse (update pointer first, then read)